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st sitronix ST7636R 65k color dot matrix lcd controller/driver ver 1.4 1/109 2006/09/06 1. introduction the ST7636R is a driver & controller lsi for 65k color graphic dot-matrix liquid crystal display systems. it generates 396 segment and 132 common driver circuits. this chip is connected directly to a microprocessor, accepts serial peripheral interface (spi) or 8-bit/16-bit parallel display data and stores in an on-chip display data ram. it performs display data ram read/write operation with no externa l operating clock to minimize power consumption. in addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. 2. features driver output circuits ? 396 segment outputs / 132 common outputs applicable duty ratios ? various partial display ? partial window moving & data scrolling gray-scale display ? 4frc & 31 pwm function circuit to display ? 64 gray-scale display. on-chip display data ram ? capacity: 132 x 132 x 16 =278,784bits ? 4k colors (rgb)=(444) mode ? 65k colors (rgb)=(565) mode ? truncated 262k colors (rgb)=(666) mode ? truncated 16m colors (rgb)=(888) mode microprocessor interface ? 8/16-bit parallel bi-directional interface with 6800-series or 8080-series ? 4-line serial interface (4-line-sif) ? 3-line serial interface (3-line-sif) on-chip low power analog circuit ? on-chip oscillator circuit ? voltage converter (x2, x3, x4, x5, x6, x7, x8) ? voltage regulator (temperature gradient -0.15%/ j ) ? on-chip electronic contrast control function (406 steps) ? voltage follower (lcd bias: 1/5 to 1/12) operating voltage range ? supply voltage (vdd, vdd1): 1.8 to 3.3v (vdd2, vdd3, vdd4, vdd5): 2.4 to 3.3v ? lcd driving voltage (vop = v0 - vss): 3.76 to 18.0 v ? the suggested value of v0 is 12~15 v under bias =1/11 or 1/12 lcd driving voltage (eeprom) ? to store contrast adjustment value for better display ? to store adjustment value for best crosstalk performance eeprom adjustment voltage ? when writing value to eeprom, vdd2~vdd5 must follow as: when booster x6: vdd2~vdd5 =3.3v when booster x7: vdd2~vdd5 =2.8v~3.0v and booster:on, regulator: off, follower: off, display off (refer eeprom flow, page.43 , page.105) package type ? application for cog ST7636R 6800 , 8080 ,4-line , 3-line interface
ST7636R ver 1.4 2/109 2006/09/06 3. ST7636R pad arrangement (cog) chip size : with seal ring & scribe line : 15,090 um x 1,410um bump pitch: pad no 1 ~ 484, 605~648: 31 um (com/seg) pad no 485 ~ 604: 110 um (o) bump size: pad no.1~440, 479~484, 605~610 : 16 um(x) x 118 um(y) pad no.441~ 478, 611~648: 118 um(x) x 16 um(y) pad n0. 485~604, dummy pad: 90 um(x) x 40 um(y) bump height: 15 um chip thickness: 400 um
ST7636R ver 1.4 3/109 2006/09/06 4. pad center coordinates pin name pad no. csel=0 csel=1 x y 001 com[44] com[88] 7227.3 598.0 002 com[45] com[90] 7196.3 598.0 003 com[46] com[92] 7165.3 598.0 004 com[47] com[94] 7134.3 598.0 005 com[48] com[96] 7103.3 598.0 006 com[49] com[98] 7072.3 598.0 007 com[50] com[100] 7041.3 598.0 008 com[51] com[102] 7010.3 598.0 009 com[52] com[104] 6979.3 598.0 010 com[53] com[106] 6948.3 598.0 011 com[54] com[108] 6917.3 598.0 012 com[55] com[110] 6886.3 598.0 013 com[56] com[112] 6855.3 598.0 014 com[57] com[114] 6824.3 598.0 015 com[58] com[116] 6793.3 598.0 016 com[59] com[118] 6762.3 598.0 017 com[60] com[120] 6731.3 598.0 018 com[61] com[122] 6700.3 598.0 019 com[62] com[124] 6669.3 598.0 020 com[63] com[126] 6638.3 598.0 021 com[64] com[128] 6607.3 598.0 022 com[65] com[130] 6576.3 598.0 023 seg[395] 6122.5 598.0 024 seg[394] 6091.5 598.0 025 seg[393] 6060.5 598.0 026 seg[392] 6029.5 598.0 027 seg[391] 5998.5 598.0 028 seg[390] 5967.5 598.0 029 seg[389] 5936.5 598.0 030 seg[388] 5905.5 598.0 031 seg[387] 5874.5 598.0 032 seg[386] 5843.5 598.0 033 seg[385] 5812.5 598.0 034 seg[384] 5781.5 598.0 pin name pad no. csel=0 csel=1 x y 035 seg[383] 5750.5 598.0 036 seg[382] 5719.5 598.0 037 seg[381] 5688.5 598.0 038 seg[380] 5657.5 598.0 039 seg[379] 5626.5 598.0 040 seg[378] 5595.5 598.0 041 seg[377] 5564.5 598.0 042 seg[376] 5533.5 598.0 043 seg[375] 5502.5 598.0 044 seg[374] 5471.5 598.0 045 seg[373] 5440.5 598.0 046 seg[372] 5409.5 598.0 047 seg[371] 5378.5 598.0 048 seg[370] 5347.5 598.0 049 seg[369] 5316.5 598.0 050 seg[368] 5285.5 598.0 051 seg[367] 5254.5 598.0 052 seg[366] 5223.5 598.0 053 seg[365] 5192.5 598.0 054 seg[364] 5161.5 598.0 055 seg[363] 5130.5 598.0 056 seg[362] 5099.5 598.0 057 seg[361] 5068.5 598.0 058 seg[360] 5037.5 598.0 059 seg[359] 5006.5 598.0 060 seg[358] 4975.5 598.0 061 seg[357] 4944.5 598.0 062 seg[356] 4913.5 598.0 063 seg[355] 4882.5 598.0 064 seg[354] 4851.5 598.0 065 seg[353] 4820.5 598.0 066 seg[352] 4789.5 598.0 067 seg[351] 4758.5 598.0 068 seg[350] 4727.5 598.0
ST7636R ver 1.4 4/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 069 seg[349] 4696.5 598.0 070 seg[348] 4665.5 598.0 071 seg[347] 4634.5 598.0 072 seg[346] 4603.5 598.0 073 seg[345] 4572.5 598.0 074 seg[344] 4541.5 598.0 075 seg[343] 4510.5 598.0 076 seg[342] 4479.5 598.0 077 seg[341] 4448.5 598.0 078 seg[340] 4417.5 598.0 079 seg[339] 4386.5 598.0 080 seg[338] 4355.5 598.0 081 seg[337] 4324.5 598.0 082 seg[336] 4293.5 598.0 083 seg[335] 4262.5 598.0 084 seg[334] 4231.5 598.0 085 seg[333] 4200.5 598.0 086 seg[332] 4169.5 598.0 087 seg[331] 4138.5 598.0 088 seg[330] 4107.5 598.0 089 seg[329] 4076.5 598.0 090 seg[328] 4045.5 598.0 091 seg[327] 4014.5 598.0 092 seg[326] 3983.5 598.0 093 seg[325] 3952.5 598.0 094 seg[324] 3921.5 598.0 095 seg[323] 3890.5 598.0 096 seg[322] 3859.5 598.0 097 seg[321] 3828.5 598.0 098 seg[320] 3797.5 598.0 099 seg[319] 3766.5 598.0 100 seg[318] 3735.5 598.0 101 seg[317] 3704.5 598.0 102 seg[316] 3673.5 598.0 103 seg[315] 3642.5 598.0 pin name pad no. csel=0 csel=1 x y 104 seg[314] 3611.5 598.0 105 seg[313] 3580.5 598.0 106 seg[312] 3549.5 598.0 107 seg[311] 3518.5 598.0 108 seg[310] 3487.5 598.0 109 seg[309] 3456.5 598.0 110 seg[308] 3425.5 598.0 111 seg[307] 3394.5 598.0 112 seg[306] 3363.5 598.0 113 seg[305] 3332.5 598.0 114 seg[304] 3301.5 598.0 115 seg[303] 3270.5 598.0 116 seg[302] 3239.5 598.0 117 seg[301] 3208.5 598.0 118 seg[300] 3177.5 598.0 119 seg[299] 3146.5 598.0 120 seg[298] 3115.5 598.0 121 seg[297] 3084.5 598.0 122 seg[296] 3053.5 598.0 123 seg[295] 3022.5 598.0 124 seg[294] 2991.5 598.0 125 seg[293] 2960.5 598.0 126 seg[292] 2929.5 598.0 127 seg[291] 2898.5 598.0 128 seg[290] 2867.5 598.0 129 seg[289] 2836.5 598.0 130 seg[288] 2805.5 598.0 131 seg[287] 2774.5 598.0 132 seg[286] 2743.5 598.0 133 seg[285] 2712.5 598.0 134 seg[284] 2681.5 598.0 135 seg[283] 2650.5 598.0 136 seg[282] 2619.5 598.0 137 seg[281] 2588.5 598.0 138 seg[280] 2557.5 598.0
ST7636R ver 1.4 5/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 139 seg[279] 2526.5 598.0 140 seg[278] 2495.5 598.0 141 seg[277] 2464.5 598.0 142 seg[276] 2433.5 598.0 143 seg[275] 2402.5 598.0 144 seg[274] 2371.5 598.0 145 seg[273] 2340.5 598.0 146 seg[272] 2309.5 598.0 147 seg[271] 2278.5 598.0 148 seg[270] 2247.5 598.0 149 seg[269] 2216.5 598.0 150 seg[268] 2185.5 598.0 151 seg[267] 2154.5 598.0 152 seg[266] 2123.5 598.0 153 seg[265] 2092.5 598.0 154 seg[264] 2061.5 598.0 155 seg[263] 2030.5 598.0 156 seg[262] 1999.5 598.0 157 seg[261] 1968.5 598.0 158 seg[260] 1937.5 598.0 159 seg[259] 1906.5 598.0 160 seg[258] 1875.5 598.0 161 seg[257] 1844.5 598.0 162 seg[256] 1813.5 598.0 163 seg[255] 1782.5 598.0 164 seg[254] 1751.5 598.0 165 seg[253] 1720.5 598.0 166 seg[252] 1689.5 598.0 167 seg[251] 1658.5 598.0 168 seg[250] 1627.5 598.0 169 seg[249] 1596.5 598.0 170 seg[248] 1565.5 598.0 171 seg[247] 1534.5 598.0 172 seg[246] 1503.5 598.0 173 seg[245] 1472.5 598.0 pin name pad no. csel=0 csel=1 x y 174 seg[244] 1441.5 598.0 175 seg[243] 1410.5 598.0 176 seg[242] 1379.5 598.0 177 seg[241] 1348.5 598.0 178 seg[240] 1317.5 598.0 179 seg[239] 1286.5 598.0 180 seg[238] 1255.5 598.0 181 seg[237] 1224.5 598.0 182 seg[236] 1193.5 598.0 183 seg[235] 1162.5 598.0 184 seg[234] 1131.5 598.0 185 seg[233] 1100.5 598.0 186 seg[232] 1069.5 598.0 187 seg[231] 1038.5 598.0 188 seg[230] 1007.5 598.0 189 seg[229] 976.5 598.0 190 seg[228] 945.5 598.0 191 seg[227] 914.5 598.0 192 seg[226] 883.5 598.0 193 seg[225] 852.5 598.0 194 seg[224] 821.5 598.0 195 seg[223] 790.5 598.0 196 seg[222] 759.5 598.0 197 seg[221] 728.5 598.0 198 seg[220] 697.5 598.0 199 seg[219] 666.5 598.0 200 seg[218] 635.5 598.0 201 seg[217] 604.5 598.0 202 seg[216] 573.5 598.0 203 seg[215] 542.5 598.0 204 seg[214] 511.5 598.0 205 seg[213] 480.5 598.0 206 seg[212] 449.5 598.0 207 seg[211] 418.5 598.0 208 seg[210] 387.5 598.0
ST7636R ver 1.4 6/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 209 seg[209] 356.5 598.0 210 seg[208] 325.5 598.0 211 seg[207] 294.5 598.0 212 seg[206] 263.5 598.0 213 seg[205] 232.5 598.0 214 seg[204] 201.5 598.0 215 seg[203] 170.5 598.0 216 seg[202] 139.5 598.0 217 seg[201] 108.5 598.0 218 seg[200] 77.5 598.0 219 seg[199] 46.5 598.0 220 seg[198] 15.5 598.0 221 seg[197] -15.5 598.0 222 seg[196] -46.5 598.0 223 seg[195] -77.5 598.0 224 seg[194] -108.5 598.0 225 seg[193] -139.5 598.0 226 seg[192] -170.5 598.0 227 seg[191] -201.5 598.0 228 seg[190] -232.5 598.0 229 seg[189] -263.5 598.0 230 seg[188] -294.5 598.0 231 seg[187] -325.5 598.0 232 seg[186] -356.5 598.0 233 seg[185] -387.5 598.0 234 seg[184] -418.5 598.0 235 seg[183] -449.5 598.0 236 seg[182] -480.5 598.0 237 seg[181] -511.5 598.0 238 seg[180] -542.5 598.0 239 seg[179] -573.5 598.0 240 seg[178] -604.5 598.0 241 seg[177] -635.5 598.0 242 seg[176] -666.5 598.0 243 seg[175] -697.5 598.0 pin name pad no. csel=0 csel=1 x y 244 seg[174] -728.5 598.0 245 seg[173] -759.5 598.0 246 seg[172] -790.5 598.0 247 seg[171] -821.5 598.0 248 seg[170] -852.5 598.0 249 seg[169] -883.5 598.0 250 seg[168] -914.5 598.0 251 seg[167] -945.5 598.0 252 seg[166] -976.5 598.0 253 seg[165] -1007.5 598.0 254 seg[164] -1038.5 598.0 255 seg[163] -1069.5 598.0 256 seg[162] -1100.5 598.0 257 seg[161] -1131.5 598.0 258 seg[160] -1162.5 598.0 259 seg[159] -1193.5 598.0 260 seg[158] -1224.5 598.0 261 seg[157] -1255.5 598.0 262 seg[156] -1286.5 598.0 263 seg[155] -1317.5 598.0 264 seg[154] -1348.5 598.0 265 seg[153] -1379.5 598.0 266 seg[152] -1410.5 598.0 267 seg[151] -1441.5 598.0 268 seg[150] -1472.5 598.0 269 seg[149] -1503.5 598.0 270 seg[148] -1534.5 598.0 271 seg[147] -1565.5 598.0 272 seg[146] -1596.5 598.0 273 seg[145] -1627.5 598.0 274 seg[144] -1658.5 598.0 275 seg[143] -1689.5 598.0 276 seg[142] -1720.5 598.0 277 seg[141] -1751.5 598.0 278 seg[140] -1782.5 598.0
ST7636R ver 1.4 7/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 279 seg[139] -1813.5 598.0 280 seg[138] -1844.5 598.0 281 seg[137] -1875.5 598.0 282 seg[136] -1906.5 598.0 283 seg[135] -1937.5 598.0 284 seg[134] -1968.5 598.0 285 seg[133] -1999.5 598.0 286 seg[132] -2030.5 598.0 287 seg[131] -2061.5 598.0 288 seg[130] -2092.5 598.0 289 seg[129] -2123.5 598.0 290 seg[128] -2154.5 598.0 291 seg[127] -2185.5 598.0 292 seg[126] -2216.5 598.0 293 seg[125] -2247.5 598.0 294 seg[124] -2278.5 598.0 295 seg[123] -2309.5 598.0 296 seg[122] -2340.5 598.0 297 seg[121] -2371.5 598.0 298 seg[120] -2402.5 598.0 299 seg[119] -2433.5 598.0 300 seg[118] -2464.5 598.0 301 seg[117] -2495.5 598.0 302 seg[116] -2526.5 598.0 303 seg[115] -2557.5 598.0 304 seg[114] -2588.5 598.0 305 seg[113] -2619.5 598.0 306 seg[112] -2650.5 598.0 307 seg[111] -2681.5 598.0 308 seg[110] -2712.5 598.0 309 seg[109] -2743.5 598.0 310 seg[108] -2774.5 598.0 311 seg[107] -2805.5 598.0 312 seg[106] -2836.5 598.0 313 seg[105] -2867.5 598.0 pin name pad no. csel=0 csel=1 x y 314 seg[104] -2898.5 598.0 315 seg[103] -2929.5 598.0 316 seg[102] -2960.5 598.0 317 seg[101] -2991.5 598.0 318 seg[100] -3022.5 598.0 319 seg[99] -3053.5 598.0 320 seg[98] -3084.5 598.0 321 seg[97] -3115.5 598.0 322 seg[96] -3146.5 598.0 323 seg[95] -3177.5 598.0 324 seg[94] -3208.5 598.0 325 seg[93] -3239.5 598.0 326 seg[92] -3270.5 598.0 327 seg[91] -3301.5 598.0 328 seg[90] -3332.5 598.0 329 seg[89] -3363.5 598.0 330 seg[88] -3394.5 598.0 331 seg[87] -3425.5 598.0 332 seg[86] -3456.5 598.0 333 seg[85] -3487.5 598.0 334 seg[84] -3518.5 598.0 335 seg[83] -3549.5 598.0 336 seg[82] -3580.5 598.0 337 seg[81] -3611.5 598.0 338 seg[80] -3642.5 598.0 339 seg[79] -3673.5 598.0 340 seg[78] -3704.5 598.0 341 seg[77] -3735.5 598.0 342 seg[76] -3766.5 598.0 343 seg[75] -3797.5 598.0 344 seg[74] -3828.5 598.0 345 seg[73] -3859.5 598.0 346 seg[72] -3890.5 598.0 347 seg[71] -3921.5 598.0 348 seg[70] -3952.5 598.0
ST7636R ver 1.4 8/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 349 seg[69] -3983.5 598.0 350 seg[68] -4014.5 598.0 351 seg[67] -4045.5 598.0 352 seg[66] -4076.5 598.0 353 seg[65] -4107.5 598.0 354 seg[64] -4138.5 598.0 355 seg[63] -4169.5 598.0 356 seg[62] -4200.5 598.0 357 seg[61] -4231.5 598.0 358 seg[60] -4262.5 598.0 359 seg[59] -4293.5 598.0 360 seg[58] -4324.5 598.0 361 seg[57] -4355.5 598.0 362 seg[56] -4386.5 598.0 363 seg[55] -4417.5 598.0 364 seg[54] -4448.5 598.0 365 seg[53] -4479.5 598.0 366 seg[52] -4510.5 598.0 367 seg[51] -4541.5 598.0 368 seg[50] -4572.5 598.0 369 seg[49] -4603.5 598.0 370 seg[48] -4634.5 598.0 371 seg[47] -4665.5 598.0 372 seg[46] -4696.5 598.0 373 seg[45] -4727.5 598.0 374 seg[44] -4758.5 598.0 375 seg[43] -4789.5 598.0 376 seg[42] -4820.5 598.0 377 seg[41] -4851.5 598.0 378 seg[40] -4882.5 598.0 379 seg[39] -4913.5 598.0 380 seg[38] -4944.5 598.0 381 seg[37] -4975.5 598.0 382 seg[36] -5006.5 598.0 383 seg[35] -5037.5 598.0 pin name pad no. csel=0 csel=1 x y 384 seg[34] -5068.5 598.0 385 seg[33] -5099.5 598.0 386 seg[32] -5130.5 598.0 387 seg[31] -5161.5 598.0 388 seg[30] -5192.5 598.0 389 seg[29] -5223.5 598.0 390 seg[28] -5254.5 598.0 391 seg[27] -5285.5 598.0 392 seg[26] -5316.5 598.0 393 seg[25] -5347.5 598.0 394 seg[24] -5378.5 598.0 395 seg[23] -5409.5 598.0 396 seg[22] -5440.5 598.0 397 seg[21] -5471.5 598.0 398 seg[20] -5502.5 598.0 399 seg[19] -5533.5 598.0 400 seg[18] -5564.5 598.0 401 seg[17] -5595.5 598.0 402 seg[16] -5626.5 598.0 403 seg[15] -5657.5 598.0 404 seg[14] -5688.5 598.0 405 seg[13] -5719.5 598.0 406 seg[12] -5750.5 598.0 407 seg[11] -5781.5 598.0 408 seg[10] -5812.5 598.0 409 seg[9] -5843.5 598.0 410 seg[8] -5874.5 598.0 411 seg[7] -5905.5 598.0 412 seg[6] -5936.5 598.0 413 seg[5] -5967.5 598.0 414 seg[4] -5998.5 598.0 415 seg[3] -6029.5 598.0 416 seg[2] -6060.5 598.0 417 seg[1] -6091.5 598.0 418 seg[0] -6122.5 598.0
ST7636R ver 1.4 9/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 419 com[66] com[131] -6576.3 598.0 420 com[67] com[129] -6607.3 598.0 421 com[68] com[127] -6638.3 598.0 422 com[69] com[125] -6669.3 598.0 423 com[70] com[123] -6700.3 598.0 424 com[71] com[121] -6731.3 598.0 425 com[72] com[119] -6762.3 598.0 426 com[73] com[117] -6793.3 598.0 427 com[74] com[115] -6824.3 598.0 428 com[75] com[113] -6855.3 598.0 429 com[76] com[111] -6886.3 598.0 430 com[77] com[109] -6917.3 598.0 431 com[78] com[107] -6948.3 598.0 432 com[79] com[105] -6979.3 598.0 433 com[80] com[103] -7010.3 598.0 434 com[81] com[101] -7041.3 598.0 435 com[82] com[99] -7072.3 598.0 436 com[83] com[97] -7103.3 598.0 437 com[84] com[95] -7134.3 598.0 438 com[85] com[93] -7165.3 598.0 439 com[86] com[91] -7196.3 598.0 440 com[87] com[89] -7227.3 598.0 441 com[88] com[87] -7438.0 563.5 442 com[89] com[85] -7438.0 532.5 443 com[90] com[83] -7438.0 501.5 444 com[91] com[81] -7438.0 470.5 445 com[92] com[79] -7438.0 439.5 446 com[93] com[77] -7438.0 408.5 447 com[94] com[75] -7438.0 377.5 448 com[95] com[73] -7438.0 346.5 449 com[96] com[71] -7438.0 315.5 450 com[97] com[69] -7438.0 284.5 451 com[98] com[67] -7438.0 253.5 452 com[99] com[65] -7438.0 222.5 453 com[100] com[63] -7438.0 191.5 pin name pad no. csel=0 csel=1 x y 454 com[101] com[61] -7438.0 160.5 455 com[102] com[59] -7438.0 129.5 456 com[103] com[57] -7438.0 98.5 457 com[104] com[55] -7438.0 67.5 458 com[105] com[53] -7438.0 36.5 459 com[106] com[51] -7438.0 5.5 460 com[107] com[49] -7438.0 -25.5 461 com[108] com[47] -7438.0 -56.5 462 com[109] com[45] -7438.0 -87.5 463 com[110] com[43] -7438.0 -118.5 464 com[111] com[41] -7438.0 -149.5 465 com[112] com[39] -7438.0 -180.5 466 com[113] com[37] -7438.0 -211.5 467 com[114] com[35] -7438.0 -242.5 468 com[115] com[33] -7438.0 -273.5 469 com[116] com[31] -7438.0 -304.5 470 com[117] com[29] -7438.0 -335.5 471 com[118] com[27] -7438.0 -366.5 472 com[119] com[25] -7438.0 -397.5 473 com[120] com[23] -7438.0 -428.5 474 com[121] com[21] -7438.0 -459.5 475 com[122] com[19] -7438.0 -490.5 476 com[123] com[17] -7438.0 -521.5 477 com[124] com[15] -7438.0 -552.5 478 com[125] com[13] -7438.0 -583.5 479 com[126] com[11] -7227.3 -598.0 480 com[127] com[9] -7196.3 -598.0 481 com[128] com[7] -7165.3 -598.0 482 com[129] com[5] -7134.3 -598.0 483 com[130] com[3] -7103.3 -598.0 484 com[131] com[1] -7072.3 -598.0 485 vdd -6100.1 -634.0 486 cl -5990.1 -634.0 487 cls -5880.1 -634.0 488 vss -5770.1 -634.0
ST7636R ver 1.4 10/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 489 vdd -5660.1 -634.0 490 a0 -5550.1 -634.0 491 rw_wr -5440.1 -634.0 492 vss -5330.1 -634.0 493 vdd -5220.1 -634.0 494 d0 -5110.1 -634.0 495 d1 -5000.1 -634.0 496 d2 -4890.1 -634.0 497 d3 -4780.1 -634.0 498 d4 -4670.1 -634.0 499 d5 -4560.1 -634.0 500 d6 -4450.1 -634.0 501 d7 -4340.1 -634.0 502 vss -4230.1 -634.0 503 vdd -4120.1 -634.0 504 d8 -4010.1 -634.0 505 d9 -3900.1 -634.0 506 d10 -3790.1 -634.0 507 d11 -3680.1 -634.0 508 d12 -3570.1 -634.0 509 d13 -3460.1 -634.0 510 d14 -3350.1 -634.0 511 d15 -3240.1 -634.0 512 vss -3130.1 -634.0 513 vdd -3020.1 -634.0 514 e_rd -2910.1 -634.0 515 rst -2800.1 -634.0 516 vss -2690.1 -634.0 517 vdd -2580.1 -634.0 518 csel -2470.1 -634.0 519 intrs -2360.1 -634.0 520 if1 -2250.1 -634.0 521 if2 -2140.1 -634.0 522 if3 -2030.1 -634.0 523 vss -1920.1 -634.0 pin name pad no. csel=0 csel=1 x y 524 vdd -1810.1 -634.0 525 si -1700.1 -634.0 526 scl -1590.1 -634.0 527 xcs -1480.1 -634.0 528 vdd -1370.1 -634.0 529 vdd -1260.1 -634.0 530 vdd -1150.1 -634.0 531 vdd -1040.1 -634.0 532 vdd1 -930.1 -634.0 533 vdd1 -820.1 -634.0 534 vss1 -710.1 -634.0 535 vss1 -600.1 -634.0 536 vss -490.1 -634.0 537 vss -380.1 -634.0 538 vss -270.1 -634.0 539 vss -160.1 -634.0 540 vss -50.1 -634.0 541 vss 59.9 -634.0 542 vss2 169.9 -634.0 543 vss2 279.9 -634.0 544 vss2 389.9 -634.0 545 vss2 499.9 -634.0 546 vss2 609.9 -634.0 547 vss2 719.9 -634.0 548 vss2 829.9 -634.0 549 vss2 939.9 -634.0 550 vss2 1049.9 -634.0 551 vss4 1159.9 -634.0 552 vss4 1269.9 -634.0 553 vdd4 1379.9 -634.0 554 vdd4 1489.9 -634.0 555 vdd3 1599.9 -634.0 556 vdd3 1709.9 -634.0 557 vdd2 1819.9 -634.0 558 vdd2 1929.9 -634.0
ST7636R ver 1.4 11/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 559 vdd2 2039.9 -634.0 560 vdd2 2149.9 -634.0 561 vdd2 2259.9 -634.0 562 vdd2 2369.9 -634.0 563 vdd2 2479.9 -634.0 564 vdd2 2589.9 -634.0 565 vdd5 2699.9 -634.0 566 vdd5 2809.9 -634.0 567 vdd5 2919.9 -634.0 568 vdd5 3029.9 -634.0 569 tcap 3139.9 -634.0 570 c2p 3249.9 -634.0 571 c2n 3359.9 -634.0 572 c6p 3469.9 -634.0 573 c2n 3579.9 -634.0 574 c4p 3689.9 -634.0 575 c7p 3799.9 -634.0 576 c1n 3909.9 -634.0 577 c5p 4019.9 -634.0 578 c3p 4129.9 -634.0 579 c1n 4239.9 -634.0 580 c1p 4349.9 -634.0 581 vlcdin 4459.9 -634.0 582 vlcdin 4569.9 -634.0 583 vlcdin 4679.9 -634.0 584 vlcdin 4789.9 -634.0 585 vlcdin 4899.9 -634.0 586 vlcdin 5009.9 -634.0 587 vlcdout 5119.9 -634.0 588 vlcdout 5229.9 -634.0 589 vlcdout 5339.9 -634.0 590 vlcdout 5449.9 -634.0 591 vref 5559.9 -634.0 592 vr 5669.9 -634.0 593 v4 5779.9 -634.0 pin name pad no. csel=0 csel=1 x y 594 v3 5889.9 -634.0 595 v2 5999.9 -634.0 596 v1 6109.9 -634.0 597 v0out 6219.9 -634.0 598 v0out 6329.9 -634.0 599 v0out 6439.9 -634.0 600 v0out 6549.9 -634.0 601 v0in 6659.9 -634.0 602 v0in 6769.9 -634.0 603 v0in 6879.9 -634.0 604 v0in 6989.9 -634.0 605 com[0] com[0] 7072.3 -598.0 606 com[1] com[2] 7103.3 -598.0 607 com[2] com[4] 7134.3 -598.0 608 com[3] com[6] 7165.3 -598.0 609 com[4] com[8] 7196.3 -598.0 610 com[5] com[10] 7227.3 -598.0 611 com[6] com[12] 7438.0 -583.5 612 com[7] com[14] 7438.0 -552.5 613 com[8] com[16] 7438.0 -521.5 614 com[9] com[18] 7438.0 -490.5 615 com[10] com[20] 7438.0 -459.5 616 com[11] com[22] 7438.0 -428.5 617 com[12] com[24] 7438.0 -397.5 618 com[13] com[26] 7438.0 -366.5 619 com[14] com[28] 7438.0 -335.5 620 com[15] com[30] 7438.0 -304.5 621 com[16] com[32] 7438.0 -273.5 622 com[17] com[34] 7438.0 -242.5 623 com[18] com[36] 7438.0 -211.5 624 com[19] com[38] 7438.0 -180.5 625 com[20] com[40] 7438.0 -149.5 626 com[21] com[42] 7438.0 -118.5 627 com[22] com[44] 7438.0 -87.5 628 com[23] com[46] 7438.0 -56.5
ST7636R ver 1.4 12/109 2006/09/06 pin name pad no. csel=0 csel=1 x y 629 com[24] com[48] 7438.0 -25.5 630 com[25] com[50] 7438.0 5.5 631 com[26] com[52] 7438.0 36.5 632 com[27] com[54] 7438.0 67.5 633 com[28] com[56] 7438.0 98.5 634 com[29] com[58] 7438.0 129.5 635 com[30] com[60] 7438.0 160.5 636 com[31] com[62] 7438.0 191.5 637 com[32] com[64] 7438.0 222.5 638 com[33] com[66] 7438.0 253.5 pin name pad no. csel=0 csel=1 x y 639 com[34] com[68] 7438.0 284.5 640 com[35] com[70] 7438.0 315.5 641 com[36] com[72] 7438.0 346.5 642 com[37] com[74] 7438.0 377.5 643 com[38] com[76] 7438.0 408.5 644 com[39] com[78] 7438.0 439.5 645 com[40] com[80] 7438.0 470.5 646 com[41] com[82] 7438.0 501.5 647 com[42] com[84] 7438.0 532.5 648 com[43] com[86] 7438.0 563.5 dummy pad pad no. x y dummy1 -6980.1 -634.0 dummy2 -6870.1 -634.0 dummy3 -6760.1 -634.0 dummy4 -6650.1 -634.0 dummy5 -6540.1 -634.0 dummy6 -6430.1 -634.0 dummy7 -6320.1 -634.0 dummy8 -6210.1 -634.0
ST7636R ver 1.4 13/109 2006/09/06 5. block diagram v/f circuit v/r circuit segment drivers data latches common drivers common output controller circuit reset timing generator display address counter mpu interface(parallel & serial) vdd com0 to com131 seg0 to seg395 cls frc/pwm function circuit scl si display data ram (ddram) [132x132x16] address counter bus holder data register instruction register oscillator instruction decoder v/c circuit v0 in v1 v2 v3 v4 vss v0 out d0 to d15 e_rd rw_wr a0 if3 if2 if1 /rst /cs vdd1 vdd3 csel tcap vref cap1n cap2p cap2n cap3p cap4p cap5p cap6p cap7p vdd2 vss vdd5 vdd4 vr intrs cl eeprom vlcdin vlcdout
ST7636R ver 1.4 14/109 2006/09/06 6. pin description 6.1 power supply name i/o description vdd supply power supply for logic circuit vdd1 supply power supply for osc circuit vdd2 supply power supply for booster circuit vdd3 supply power supply for lcd. vdd4 supply power supply for lcd. vdd5 supply power supply for lcd. vss supply ground for logic circuit. ground system should be connected together. vss1 supply ground for osc circuit. ground system should be connected together. vss2 supply ground for booster circuit. ground system should be connected together. vss4 supply ground for lcd. ground system should be connected together. vlcd out supply if the internal voltage generator is used, the vlcd in & vlcd out must be connected together. if an external supply is used, this pin must be left open. vlcd in supply an external lcd supply voltage can be supplied using the vlcd in pad. in this case, vlcd out has to be left open, and the internal voltage generator has to be programmed to zero. (set register vc=0) v0in v0 out v1 v2 v3 v4 i/o lcd driver supply voltages v0in & v0out should be connected together. voltages should have the following relationship; v0 ( v0in ) v1 v2 v3 v4 vss, v4 < 2.3v when the internal power circuit is active, these voltages are generated as following table according to the state of lcd bias. lcd bias v1 v2 v3 v4 1/n bias (n-1) / n x v0 (n-2) / n x v0 (2/n) x v0 (1/n) x v0 note: n = 5 to 12 6.2 lcd power supply pins pin name i/o function cap1n o dc/dc voltage converter. connect capacitors between this terminal and the cap1p, cap3p, cap5p, cap7p terminal. cap2n o dc/dc voltage converter. connect capacitors between this terminal and the cap2p, cap4p, cap6p terminal. cap1p o dc/dc voltage converter. connect a capacitor between this terminal and the cap1n terminal. cap2p o dc/dc voltage converter. connect a capacitor between this terminal and the cap2n terminal. cap3p o dc/dc voltage converter. connect a capacitor between this terminal and the cap1n terminal. cap4p o dc/dc voltage converter. connect a capacitor between this terminal and the cap2n terminal.
ST7636R ver 1.4 15/109 2006/09/06 cap5p o dc/dc voltage converter. connect a capacitor between this terminal and the cap1n terminal. cap6p o dc/dc voltage converter. connect a capacitor between this terminal and the cap2n terminal. cap7p o dc/dc voltage converter. connect a capacitor between this terminal and the cap1n terminal. vref o reference voltage output for monitor only. left it opened. vr i reference voltage output for monitor only. left it opened. 6.3 system control name i/o description cls i when using internal clock oscillator, connect cls to vdd. when using external clock oscillator, connect cls to vss. cl i/o when using internal clock oscillator, it?s oscillator output. when using external clock oscillator, it?s clock input. intrs i this terminal selects the resistors for the v0 voltage level adjustment. this pin should be fixed to high. csel i select common output direction. csel=?l?, com0~com65 is in one side, com66~com131 is in the opposite side. csel=?h?, com2n(even number) is in the one side, com2n+1 (odd number) is in the opposite side. tcap i/o test pin. left it opened. 6.4 microprocessor interface name i/o description rst i reset input pin when resetb is ?l?, initialization is executed. if[3:1] i parallel / serial data input select input if1 if2 if3 mpu interface type h h h 80 series 16-bit parallel h h l 80 series 8-bit parallel h l l 68 series 16-bit parallel l h h 68 series 8-bit parallel l l h 9-bit serial (3 line) l l l 8-bit serial (4 line) /cs i chip select input pins data / instruction i/o is enabled only when /cs is "l". when chip select is non-active, d0 to d15 become high impedance. a0 i register select input pin
ST7636R ver 1.4 16/109 2006/09/06 a0 = "h": d0 to d15 or si are display data a0 = "l": d0 to d15 or si are control data in 3-line or 2-line interface not let it floating, contact it to vss or vdd. rw_wr i read / write execution control pin mpu type rw_wr description 6800-series rw read / write control input pin rw = ?h? : read rw = ?l? : write 8080-series /wr write enable clock input pin the data on d0 to d15 are latched at the rising edge of the /wr signal. when in the serial interface, contact it to vss or vdd. e_rd i read / write execution control pin mpu type e_rd description 6800-series e read / write control input pin rw = ?h?: when e is ?h?, d0 to d15 are in an output status. rw = ?l?: the data on d0 to d15 are latched at the falling edge of the e signal. 8080-series /rd read enable clock input pin when /rd is ?l?, d0 to d15 are in an output status. when in the serial interface, contact it to vss or vdd. d15 to d0 i/o they connect to the standard 8-bit or 16 bit mpu bus via the 8/16 ?bit bi-directional bus. when the following interface is selected and the /cs pin is high, the following pins become high impedance. 1. in 8-bit parallel: d15-d8 are in the state of high impedance, should contact to ?h? level or ?l? level. 2. in serial interface: d15-d0 are in the state of high impedance, should contact to ?h? level or ?l? level. si i this pin is used to input serial data when the serial interface is selected.(3 line and 4 line) when not use contact it to vdd (high level). scl i this pin is used to input serial clock when the serial interface is selected. the data is converted in the rising edge. (3 line and 4 line) when not use contact it to vdd (high level). note: microprocessor interface pins should not be floating in any operation mode.
ST7636R ver 1.4 17/109 2006/09/06 6.5 lcd driver outputs name i/o description seg0 to seg395 o lcd segment driver outputs the display data and the m signal control the output voltage of segment driver. segment driver output voltage display data m (internal) normal display reverse display h h v0 v2 h l vss v3 l h v2 v0 l l v3 vss sleep in mode vss vss com0 to com131 o lcd common driver outputs the internal scanning data and m signal control the output voltage of common driver. scan data m (internal) co mmon driver output voltage h h vss h l v0 l h v1 l l v4 sleep in mode vss ST7636R i/o pin ito resister limitation pin name ito resister vref, tcap, cl, vr floating if[3:1],cls,csel,intrs no limitation vdd, vdd1~vdd5, vss, cap1n, cap2n, vlcd in , vlcd out <100 ? v0in, v0out, v1, v2, v3, v4, cap1p~7p <100 ? a0, e_rd, rw_wr, /cs, d0 ?d15, scl, si <1k ? rst <10k ? note: (1) make sure the ito resistance of com0 ~ com131 is equal, and so is it of seg0 ~ seg395. (2) all the resistance values in above table are under digital power supply is 2.8v condition.
ST7636R ver 1.4 18/109 2006/09/06 7. functional description 7.1 microprocessor interface chip select input /cs pin is for chip selection. the ST7636R can function with an mpu when /cs is "l". in case of serial interface, the internal shift register and the counter are reset. 7.1.1 selecting parallel / serial interface ST7636R has seven types of interface with an mpu, which are two serial and four parallel interfaces. this parallel or serial interface is determined by if pin as shown in table 7.1.1 . table 7.1.1 parallel / serial interface mode i/f mode pin assignment if1 if2 if3 i/f description /cs a0 e_rd rw_wr d15 to d8 d7 to d0 si scl h h h 80 serial 16-bit parallel /cs a0 /rd /wr d15 ~ d8 d7 ~ d0 -- -- h h l 80 serial 8-bit parallel /cs a0 /rd /wr -- d7 ~ d0 -- -- h l l 68 serial 16-bit parallel /cs a0 e r/w d15 ~ d8 d7 ~ d0 -- -- l h h 68 serial 8-bit parallel /cs a0 e r/w -- d7 ~ d0 -- -- l l l 8-bit spi mode (4 line) /cs a0 -- -- -- -- si scl l l h 9-bit spi mode (3 line) /cs -- -- -- -- -- si scl note: when these pins are set to any other combination, a0, e_rd and rw_wr inputs are disabled and d0 to d15 are to be high impedance. 7.1.2 8-bit or 16-bit parallel interface the ST7636R identifies the type of the data bus signals according to the combination of a0, /rd (e) and /wr (w/r) signals, as shown in table 7.1.2. table 7.1.2 parallel data transfer common 6800-series 8080-series a0 r/w e /rd /wr description h h h l h display data read out h l h h l display data write l h h l h register status read l l h h l writes to internal register (instruction) relation between data bus and gradation data ST7636R offers 4096 color display, 65k color display, truncated 262k color, and truncated 16m color. when using 4096, 65k, 262k, and 16m color, you can specify color for each of r, g, b using the palette function. use the command for switching between these modes. (1) 4096-color display (1-1) type a 4096 color display 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrrgggg 1st write d7, d6, d5, d4, d3, d2, d1, d0: bbbbrrrr 2nd write
ST7636R ver 1.4 19/109 2006/09/06 d7, d6, d5, d4, d3, d2, d1, d0: ggggbbbb 3rd write 2 pixels of data are read after the third write operation as shown, and it is written in the display ram. 2. 16-bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0: rrrrggggbbbbxxxx data is acquired through signal write operation and then written to the display ram. ?xxxx? are dummy bits, and they are ignored for display. (1-2) type b 4096 color display 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: xxxxrrrr 1st write d7, d6, d5, d4, d3, d2, d1, d0: ggggbbbb 2nd write a single pixel of data is read after the second write operation as shown, and it is written in the display ram. 2. 16-bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0: xxxxrrrrggggbbbb a single pixel of data is read and written in the display ram in a single write operation. ?xxxx? are dummy bits, and they are ignored for display. (2) 65k color input mode 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrrrggg 1st write d7, d6, d5, d4, d3, d2, d1, d0: gggbbbbb 2nd write a single pixel of data is read after the second write operation as shown, and it is written in the display ram. 2. 16-bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0: rrrrrggggggbbbbb (16 bits) data is acquired through signal write operation and then written to the display ram. (3) truncated 262k color input mode 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrrrrxx 1st write d7, d6, d5, d4, d3, d2, d1, d0: ggggggxx 2nd write d7, d6, d5, d4, d3, d2, d1, d0: bbbbbbxx 3rd write a single pixel of data is read after the third write operation as shown, and it is written in the display ram. ?x? is dummy bit, and it is ignored for display. 2. 16 bit mode
ST7636R ver 1.4 20/109 2006/09/06 d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0: rrrrrrxxggggggxx 1st write d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2 , d1, d0: bbbbbbxxxxxxxxxxxx 2nd wr ite a single pixel of data is read after the second write operation as shown, and it is written in the display ram. (4) truncated 16m color input mode 1. 8-bit mode d7, d6, d5, d4, d3, d2, d1, d0: rrrrrrrr 1st write d7, d6, d5, d4, d3, d2, d1, d0: gggggggg 2nd write d7, d6, d5, d4, d3, d2, d1, d0: bbbbbbbb 3rd write a single pixel of data is read after the third write operation as shown, and it is written in the display ram. 2. 16 bit mode d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2, d1, d0: rrrrrrrrgggggggg 1st write d15, d14, d13, d12, d11, d10, d9, d8, d7, d6, d5, d4, d3, d2 , d1, d0: bbbbbbbbxxxxxxxx 2nd write a single pixel of data is read after the second write operation as shown, and it is written in the display ram.
ST7636R ver 1.4 21/109 2006/09/06 7.1.3 8- and 9-bit serial interface the 8-bit serial interface uses four pins /cs, si, scl, and a0 to enter commands and data. meanwhile, the 9-bit serial interface uses three pins /cs, si and scl for the same purpose. data read is not available in the serial interface. data entered must be 8 bits. refer to the following chart for entering commands, parameters or gray-scale data. the relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface m ode at every gradation. (1) 8-bit serial interface (4 line ) when entering data (parameters): a0= high at the rising edge of the 8 th scl. when entering command: a0= low at the rising edge of the 8 th scl
ST7636R ver 1.4 22/109 2006/09/06 (2) 9-bit serial interface (3 line ) when entering data (parameters): si= high at the rising edge of the 1 st scl. when entering command: si= low at the rising edge of the 1 st scl. z if /cs is set to high while the 8 bits from d7 to d0 are entered, the data concerned is invalidated. before entering succeeding sets of data, you must correctly input the data concerned again. z in order to avoid data transfer error due to incoming noise, it is recommended to set /cs at high on byte basis to initialize the serial-to-parallel conversion counter and the register. z when executing the command ramwr, set /cs to high after writing the last address (after starting the 9 th pulse in case of 9-bit serial input or after starting the 8 th pulse in case of 8-bit serial input). d7 d6 d5 d4 d3 d2 d1 d0 d/c d7 /cs si scl data data d6 d/c 12 34 5 67 89 1 2 3
ST7636R ver 1.4 23/109 2006/09/06 7.2 access to ddram and internal registers ST7636R realizes high-speed data transfer because the access from mpu is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. for example, when mpu writes data to the ddram, the data is once held by the bus holder and then written to the ddram before the succeeding write cycle is started. when mpu reads data from the ddram, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. figure 7.2.1 illustrates these relations. in 80-series interface mode: n d(n) d(n+1) d(n+2) d(n+3) n d(n) d(n+1) d(n+2) d(n+3) nn+1n+2 n+3 mpu signal a0 /wr data internal signals bus holder address counter write operation /wr ndummy d(n) d(n+1) mpu signal a0 data internal signals address counter /rd n d(n) d(n+1) d(n+2) d(n+3) bus holder read operation /wr /wr /rd d(n) d(n+1) d(n+2) figure 7.2.1
ST7636R ver 1.4 24/109 2006/09/06 7.3 display data ram (ddram) 7.3.1 ddram it is 132 x 132 x 16 bits capacity ram prepared for storing dot data. you can access a desired bit by specifying the page address and column address. since display data from mcu d7 to d0 and d15 to d8 correspond to one or two pixels of rgb, data transfer related restrictions are reduced, realizing the display flexing. the ram on ST7636R is separated to a block per 4 lines to allow the display system to process data on the block basis. mpu?s read and write operations to and from the ram are performed via the i/o buffer circuit; reading of the ram for the liquid crystal drive is controlled from another separate circuit. refer to the following memory map for the ram configuration. memory map (when using the type a 4096 color. 8-bit mode,) rgbrgb rgb d0_7 d0_3 d1_7 d1_3 d2_7 d2_3 d196_3 d197_7 d197_3 d0_6 d0_2 d1_6 d1_2 d2_6 d2_2 d196_2 d197_6 d197_2 d0_5 d0_1 d1_5 d1_1 d2_5 d2_1 d196_1 d197_5 d197_1 d0_4 d0_0 d1_4 d1_0 d2_4 d2_0 d196_0 d197_4 d197_0 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb alignment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131
ST7636R ver 1.4 25/109 2006/09/06 memory map (when using the type a 4096 color. 16-bit mode,) rgbrgb rgb d0_15 d0_11 d0_7 d1_15 d1_11 d1_7 d131_15 d131_11 d131_7 d0_14 d0_10 d0_6 d1_14 d1_10 d1_6 d131_14 d131_10 d131_6 d0_13 d0_9 d0_5 d1_13 d1_9 d1_5 d131_13 d131_9 d131_5 d0_12 d0_8 d0_4 d1_12 d1_8 d1_4 d131_12 d131_8 d131_4 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb alignment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131
ST7636R ver 1.4 26/109 2006/09/06 memory map (when using the type b 4096 color. 8-bit mode,) rgbrgb rgb d0_3 d1_7 d1_3 d2_3 d3_7 d3_3 d262_3 d263_7 d263_3 d0_2 d1_6 d1_2 d2_2 d3_6 d3_2 d262_2 d263_6 d263_2 d0_1 d1_5 d1_1 d2_1 d3_5 d3_1 d262_1 d263_5 d263_1 d0_0 d1_4 d1_0 d2_0 d3_4 d3_0 d262_0 d263_4 d263_0 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb alignment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131 you can change position of r and b with datactl command.
ST7636R ver 1.4 27/109 2006/09/06 memory map (when using the type b 4096 color. 16-bit mode,) rgbrgb rgb d0_11 d0_7 d0_3 d1_11 d1_7 d1_3 d131_11 d131_7 d131_3 d0_10 d0_6 d0_2 d1_10 d1_6 d1_2 d131_10 d131_6 d131_2 d0_9 d0_5 d0_1 d1_9 d1_5 d1_1 d131_9 d131_5 d131_1 d0_8 d0_4 d0_0 d1_8 d1_4 d1_0 d131_8 d131_4 d131_0 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb alignment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131 you can change position of r and b with datactl command.
ST7636R ver 1.4 28/109 2006/09/06 memory map (when using the 65kcolor. 8-bit mode,) rgbrgb rgb d0_7 d0_2 d1_4 d2_7 d2_2 d3_4 d262_7 d262_2 d263_4 d0_6 d0_1 d1_3 d2_6 d2_1 d3_3 d262_6 d262_1 d263_3 d0_5 d0_0 d1_2 d2_5 d2_0 d3_2 d262_5 d262_0 d263_2 d0_4 d1_7 d1_1 d2_4 d3_7 d3_1 d262_4 d263_7 d263_1 d0_3 d1_6 d1_0 d2_3 d3_6 d3_0 d262_3 d263_6 d263_0 d1_5 d3_5 d263_5 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 page scan block memory map p10:0 p10:1 column scan direction p11:0 color p11:1 example: data/scan format segout 0 1 31 32 1131 rgb ali g nment ( command of data control parameter2 = 000 ) 131 130 0 0 you can change position of r and b with datactl command.
ST7636R ver 1.4 29/109 2006/09/06 memory map (when using the 65k color. 16-bit mode) rgbrgb rgb d0_15 d0_10 d0_4 d1_15 d1_10 d1_4 d131_15 d131_10 d131_4 d0_14 d0_9 d0_3 d1_14 d1_9 d1_3 d131_14 d131_9 d131_3 d0_13 d0_8 d0_2 d1_13 d1_8 d1_2 d131_13 d131_8 d131_2 d0_12 d0_7 d0_1 d1_12 d1_7 d1_1 d131_12 d131_7 d131_1 d0_11 d0_6 d0_0 d1_11 d1_6 d1_0 d131_11 d131_6 d131_0 d0_5 d1_5 d131_5 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 example: data/scan format p11:1 131 color rgb ali g nment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 you can change position of r and b with datactl command.
ST7636R ver 1.4 30/109 2006/09/06 memory map (when using the 262k/16mcolor. 8-bit mode,) rgbrgb rgb d0_7 d1_7 d2_7 d3_7 d4_7 d5_7 d393_7 d394_7 d395_7 d0_6 d1_6 d2_6 d3_6 d4_6 d5_6 d393_6 d394_6 d395_6 d0_5 d1_5 d2_5 d3_5 d4_5 d5_5 d393_5 d394_5 d395_5 d0_4 d1_4 d2_4 d3_4 d4_4 d5_4 d393_4 d394_4 d395_4 d0_3 d1_3 d2_3 d3_3 d4_3 d5_3 d393_3 d394_3 d395_3 d0_2 d1_2 d2_2 d3_2 d4_2 d5_2 d393_2 d394_2 d395_2 d0_1 d1_1 d2_1 d3_1 d4_1 d5_1 d393_1 d394_1 d395_1 d0_0 d1_0 d2_0 d3_0 d4_0 d5_0 d393_0 d394_0 d395_0 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb ali g nment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131 you can change position of r and b with datactl command.
ST7636R ver 1.4 31/109 2006/09/06 memory map (when using the 16 gray-scale, 262k/16m color. 16-bit mode) rgbrgb rgb d0_15 d0_7 d1_15 d1_ d2_7 d2_7 d176_7 d177_7 d177_7 d0_14 d0_6 d1_14 d1_6 d2_6 d2_6 d176_6 d177_6 d177_6 d0_13 d0_5 d1_13 d1_5 d2_5 d2_5 d176_5 d177_5 d177_5 d0_12 d0_4 d1_12 d1_4 d2_4 d2_4 d176_4 d177_4 d177_4 d0_11 d0_3 d1_11 d1_3 d2_3 d2_3 d176_3 d177_3 d177_3 d0_10 d0_2 d1_10 d1_2 d2_2 d2_2 d176_2 d177_2 d177_2 d0_9 d0_1 d1_9 d1_1 d2_1 d2_1 d176_1 d177_1 d177_1 d0_8 d0_0 d1_8 d1_0 d2_0 d2_0 d176_0 d177_0 d177_0 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb ali g nment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131 you can change position of r and b with datactl command.
ST7636R ver 1.4 32/109 2006/09/06 memory map (when using the 16 gray-scale, 262k/16m color. 16-bit mode) rgbrgb rgb d0_15 d0_7 d1_15 d1_ d2_7 d2_7 d176_7 d177_7 d177_7 d0_14 d0_6 d1_14 d1_6 d2_6 d2_6 d176_6 d177_6 d177_6 d0_13 d0_5 d1_13 d1_5 d2_5 d2_5 d176_5 d177_5 d177_5 d0_12 d0_4 d1_12 d1_4 d2_4 d2_4 d176_4 d177_4 d177_4 d0_11 d0_3 d1_11 d1_3 d2_3 d2_3 d176_3 d177_3 d177_3 d0_10 d0_2 d1_10 d1_2 d2_2 d2_2 d176_2 d177_2 d177_2 d0_9 d0_1 d1_9 d1_1 d2_1 d2_1 d176_1 d177_1 d177_1 d0_8 d0_0 d1_8 d1_0 d2_0 d2_0 d176_0 d177_0 d177_0 0 131 1 130 2 129 3 128 4 127 5 126 6 125 7 124 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 0 1 2 3 4 5 393 394 395 0 1 31 32 segout block page scan memory map p10:0 p10:1 130 0 color example: data/scan format rgb ali g nment ( command of data control parameter2 = 000 ) column scan direction p11:0 01 131 p11:1 131 you can change position of r and b with datactl command.
ST7636R ver 1.4 33/109 2006/09/06 7.3.2 page address control circuit this circuit is used to control the address in the page direction when mpu accesses the ddram or when reading the ddram to display image on the lcd. you can specify a scope of the page address with page address set command. when the page-direction scan is specified with datactl command and the address are incremented from the start up to the end page, the column address is incremented by 1 and the page address returns to start page. the ddram supports up to 132 lines, an d thus the total page becomes 132. in the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page address is returned to start page. using the address normal/inverse parameter of datactl command allows you to inverse the correspondence between the ddram address and command output. 7.3.3 column address control circuit this circuit is used to control the address in the column direction when mpu accesses the ddram. you can specify a scope of the column address using column address set command. when the column-direction scan is specified with datactl command and the address are incremented from the star t up to the end page, the page address is incremented by 1 and the column address returns to start column. in the read operation, too, the column address is automatically incremented by 1 and returned to start page as the end column is reached. just like the page address control circuit, using the column address normal/inverse parameter of datactl command enables to inverse the correspondence between the ddram co lumn address and segment output. this arrangement relaxes restrictions in the chip layout on the lcd module. 7.3.4 i/o buffer circuit it is the bi-directional buffer used when mpu reads or writes the ddram. since mpu?s read or write of ddram is performed independently from data output to the display data latch circuit, asynchronous access to the ddram when the lcd is turned on does not cause troubles such as flicking of the display images. 7.3.5 block address circuit the circuit associates pages on ddram with com output. ST7636R processes signals for the liquid crystal display on 4-page basis. thus, when specifying a specific area in the area scroll display or partial display, you must designate it in block. 7.3.6 display data latch circuit this circuit is used to temporarily hold display data to be output from the ddram to the seg decoder circuit. since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the ddram.
ST7636R ver 1.4 34/109 2006/09/06 7.4 area scroll display using area scroll set and scroll start set commands allows you to scroll the display screen partially. you can select any one of the following four scroll patterns. fixed area scroll area ddram 0 1 2 30 blocks =128 line 27 28 fixed area 30 scroll area 31 32 background area
ST7636R ver 1.4 35/109 2006/09/06 7.5 partial display using partial in command allows you turn on the partial display (division by line) of the screen. this mode requires less current consumption than the whole screen display, making it suitable for the equipment in the standby state. : display area (partial display area) : non-display area if the partial display region is out of the max. display range, it would be no operation -com0 -com1 -com2 -com3 -com4 -com5 -com6 -com7 -com8 -com9 -com10 -com11 -com12 -com13 -com14 -com15 -com16 -com17 -com18 -com19 -com20 -com21 -com22 -com23 figure 7.5.1 reference example for partial display
ST7636R ver 1.4 36/109 2006/09/06 -com0 -com1 -com2 -com3 -com4 -com5 -com6 -com7 -com8 -com9 -com10 -com11 -com12 -com13 -com14 -com15 -com16 -com17 -com18 -com19 -com20 -com21 -com22 -com23 figure 7.5.2 partial display (partial display duty=16,initial com0=0) -com0 -com1 -com2 -com3 -com4 -com5 -com6 -com7 -com8 -com9 -com10 -com11 -com12 -com13 -com14 -com15 -com16 -com17 -com18 -com19 -com20 -com21 -com22 -com23 figure 7.5.3 moving display (partial display duty=16,initial com0=8) 7.6 gary-scale display ST7636R incorporates a 4frc & 31 pwm function circuit to display a 64 gray-scale display. 7.7 oscillation circuit this is on-chip oscillator without external resistor. when the internal oscillator is used, cls must connect to vdd; when the external oscillator is used, cl could be input pin. this oscillator signal is used in the voltage converter and display timing generation circuit.
ST7636R ver 1.4 37/109 2006/09/06 7.8 display timing generator circuit this circuit generates some signals to be used for displaying lcd. the display clock, cl (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. the line address of on-chip ram is generated in synchronization with the display clock and the display data latch circuit latches the 132-bit display data in synchronization with the display clock. the display data, which is read to the lcd driver, is completely independent of the access to the display data ram from the microprocessor. the display clock generates an lcd ac signal (m), which enables the lcd driver to make an ac drive waveform, and also generates an internal common timing signal and start signal to the common driver. the frame signal or the line signal changes the m by setting internal instruction. driving waveform and internal timing signal are shown in figure 7.8.1. fr(internal) m(internal) com0 com1 segn cl(internal) v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd 131132123456789101112 12412512612712812913013113212345 figure 7.8.1 2-frame ac driving waveform (duty ratio: 1/132) cl(internal) fr(internal) m(internal) com0 com1 segn v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss 127128123456789101112 4 3 2 1 128 127 125 124 123 122 121 120 119 126 figure 7.8.2 n-line inversion driving waveform (n=5,duty ratio=1/128)
ST7636R ver 1.4 38/109 2006/09/06 7.9 liquid crystal drive circuit this driver circuit is configured by 132-channel common driv ers and 396-channel segment driv ers. this lcd panel driver voltage depends on the combination of display data and m signal. seg 0 1 2 3 4 com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss m com0 com1 com2 seg0 seg1 v dd v ss v lcd v 1 v 2 v 3 v 4 v ss v lcd v 1 v 2 v 3 v 4 v ss
ST7636R ver 1.4 39/109 2006/09/06 7.10 liquid crystal driver power circuit the power supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. there are voltage c onverter circuits, voltage regulator circuits, and voltage follower circuits. they are controlled by power control instruction. for details, refers to "instruction description". table 7.10.1 shows the referenced combinations in using power supply circuits. table 7.10.1 recommended power supply combinations user setup power control (vc vr vf) v/c circuits v/r circuits v/f circuits vlcd v0 v1 to v4 only the internal power supply circuits are used 1 1 1 on on on to series a capacitor to gnd to series a capacitor to gnd to series a capacitor to gnd only the voltage regulator circuits and voltage follower circuits are used 0 1 1 off on on external input to series a capacitor to gnd to series a capacitor to gnd only the voltage follower circuits are used 0 0 1 off off on open external input to series a capacitor to gnd only the external power supply circuits are used 0 0 0 off off off open external input external input
ST7636R ver 1.4 40/109 2006/09/06 7.10.1 voltage converter circuits the step-up voltage circuits
ST7636R ver 1.4 41/109 2006/09/06 7.10.2 voltage regulator circuits set vop (setvop) the set vop function is used to program the optimum lcd supply voltage v0. setvop reset state of vop[8:0] is 257dec = 13.88v. the vop value is programmed via the vop[8:0] register. v0=a+( vop[8:6]vop[5:0]) ?d b ex:vop[5:0]=000001, vop[8:6]=100 vop [8:0]=100000001 3.6+257x0.04=13.88 z a is a fixed constant value (see table 7.10.2). z b is a fixed constant value (see table 7.10.2). z vop[8:0] is the programmed vop value. the programming range for vop[8:0] is 5 to 410 (19ahex). z vop[5:0] is the set contrast value which can be set via the command setvop and eeprom.(see command volup & voldown) z table 7.10.2 symbol value unit a 3.6 v b 0.04 v the vop[8:0] value must be in the vop programming range as given in figure 7.10.2. evaluating equation (1), values outside the programming range indicated in figure 7.10.2 may result. calculated values below 4 will be mapped to vop[8:0] = 4, resulting vop[8:0] values higher than 410 will be mapped to vop[8:0] = 410. (sitronix suggests that the vop range is equal 4.5v to 18v.
ST7636R ver 1.4 42/109 2006/09/06 figure 7.10.2 vop programming range as the programming range for internal generated v0 voltage allows itself value above the max voltage (18v). so users have to ensure, under all conditions, like setting the vpr register and the temperature compensation, the v0 voltage must remaine below 18v including all tolerances.
ST7636R ver 1.4 43/109 2006/09/06 7.10.3 eeprom setting flow eeprom setting flow (detail flow chart and its application programs, refer page.104) the ST7636R provide the write and read function to write the electronic control value and built-in resistance ratio into and read them from the built-in eeprom. using the write and read functions, you can store these values appropriate to each lcd panel. this function is very convenient for user in setting from some different panel?s voltage. but using this function must attend the setting procedure. please see the following diagram. note1: this setting flow is used for lcm assembler. note2: when writing value to eeprom, the voltage of vdd2~vdd5 (analog power) = 2.8v~3.0v when booster x7, and vdd2~vdd5 (analog power) = 3.3v when booster x6. note3: when writing value to eeprom, the booster must turn on, regulator and follower must turn off, and display also must turn off. note4: when writing value to eeprom, the voltage of vlcd must be more than 18v (booster efficiency must be concerned). note5: to avoid some errors during ic operati on, eeprom shouldn?t be written without preceding loading correctly register values from eeprom. note6: if the eeprom is exposed to a high temperature for hours, data in the memory cell may probably be lost before the data retention guarantee period. to re tain data in the memory cell, keep the mamory cell below 90 j . the data retention guarantee period is specified including the retention period. figure 7.10.5 ec value control for different modules by loading eeprom offset
ST7636R ver 1.4 44/109 2006/09/06 7.11 reset circuit when power is turned on input power (vdd1~vdd5) be sure to apply power-on reset (reset=low) < display setting 1 > display control (disctl) setting clock dividing ratio : duty setting : setting reverse rotation number of line : common scan direction (comscn) setting scan direction : oscillation on (oscon) : sleep-out (slipout) : < power supply setting > electronic volume control (volctr) setting volume value : setting built-in resistance value : power control (pwrctr) setting operation of power supply circuit : < display setting 2 > normal rotation of display (disnor) / inversion of display (disinv) : partial-in (ptlin) / partial-out (plout) setting fix area : area scroll set (ascset) setting area scroll region : setting area scroll type : scroll start set (scstart) setting scroll start address : < display setting 3 > data control (datctl) setting normal radiation / inversion of page address : setting normal radiation / inversion of column address : << state after reset >> 2 divisions 1/4 11h reverse rotations com0 ? com65, com66 ? com131 oscillation off sleep-in << state after reset >> 0 0 (3.76) all off << state after reset >> normal rotation of display partial-out 0 full-screen scroll 0 << state after reset >> normal rotation normal rotation
ST7636R ver 1.4 45/109 2006/09/06 setting direction of address scanner : setting rgb arrangement : setting gradation : 65k-color position set (rgbset8) setting color position at 65k-color : < ram setting > page address set (paset) setting start page address : setting end page address : column address set (paset) setting start column address : setting end column address : < ram write > memory write command (ramwr) writing displayed data : repeat as many as the number needed and exit by entering other command. < waiting (approximately 100ms) > wait until the power supply voltage has stabilized. enter the power supply control comma nd first, then wait at least 100ms before entering the display on command when the built-in power supply circuit operates. if you do not wait, an unwanted display may appear on the liquid crystal panel. display on (dison) : column direction rgb 65k all 0 << state after reset >> 0 0 0 0 << state after reset >> display off note: 1. if changes are unnecessary after reset, command input is unnecessary. 2. detail initial program please refer page.70
ST7636R ver 1.4 46/109 2006/09/06 8. commands 8.1 command table ext=0 command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function hex parameter inde x dison 0 1 0 1 0 1 0 1 1 1 1 display on af none 1 disoff 0 1 0 1 0 1 0 1 1 1 0 display off ae none 2 disnor 0 1 0 1 0 1 0 0 1 1 0 normal display a6 none 3 disinv 0 1 0 1 0 1 0 0 1 1 1 inverse display a7 none 4 comscn 0 1 0 1 0 1 1 1 0 1 1 com scan direction bb 1 byte 5 disctr1 0 1 0 1 1 0 0 1 0 1 0 display control_1 ca 3 byte 6 slpp 0 1 0 0 0 0 0 0 1 0 0 sleep in/out preparation 04 1 byte 7 slpin 0 1 0 1 0 0 1 0 1 0 1 sleep in 95 none 8 slpout 0 1 0 1 0 0 1 0 1 0 0 sleep out 94 none 9 paset 0 1 0 0 1 1 1 0 1 0 1 page address set 75 2 byte 10 caset 0 1 0 0 0 0 1 0 1 0 1 column address set 15 2 byte 11 datctl 0 1 0 1 0 1 1 1 1 0 0 data scan direction bc 3 byte 12 ramwr 0 1 0 0 1 0 1 1 1 0 0 writing to memory 5c data 13 ramrd 0 1 0 0 1 0 1 1 1 0 1 reading from memory 5d data 14 pltin 0 1 0 1 0 1 0 1 0 0 0 partial display in a8 2 byte 15 pltout 0 1 0 1 0 1 0 1 0 0 1 partial display out a9 none 16 rmwin 0 1 0 1 1 1 0 0 0 0 0 read modify write in e0 none 17 rmwout 0 1 0 1 1 1 0 1 1 1 0 read modify write out ee none 18 ascset 0 1 0 1 0 1 0 1 0 1 0 area scroll set aa 4 byte 19 scstart 0 1 0 1 0 1 0 1 0 1 1 scroll start set ab 1 byte 20 oscon 0 1 0 1 1 0 1 0 0 0 1 internal osc on d1 none 21 oscoff 0 1 0 1 1 0 1 0 0 1 0 internal osc off d2 none 22 pwrctl 0 1 0 0 0 1 0 0 0 0 0 power control 20 1 byte 23 volctr 0 1 0 1 0 0 0 0 0 0 1 ec control 81 2 byte 24 volup 0 1 0 1 1 0 1 0 1 1 0 ec increase 1 d6 none 25 voldown 0 1 0 1 1 0 1 0 1 1 1 ec decrease 1 d7 none 26 stread 0 0 1 status read status read 27 epsrrd1 0 1 0 0 1 1 1 1 1 0 0 read register1 7c none 28 epsrrd2 0 1 0 0 1 1 1 1 1 0 1 read register2 7d none 29 nop 0 1 0 0 0 1 0 0 1 0 1 nop instruction 25 none 30 eeok 0 1 0 0 0 0 0 0 1 1 1 eeprom function start 07 1 byte 31 reserved 0 1 0 1 0 0 0 0 0 1 0 do not use 82 32 ausam 0 1 0 0 1 1 0 0 0 0 0 auto-sampling 60 1 byte 33
ST7636R ver 1.4 47/109 2006/09/06 ext=1 or ext=0 command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function hex parameter index ext in 0 1 0 0 0 1 1 0 0 0 0 ext=0 set 30 none -- ext out 0 1 0 0 0 1 1 0 0 0 1 ext=1 set 31 none -- ext=1 command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function hex parameter inde x frame1 set 0 1 0 0 0 1 0 0 0 0 0 frame 1 pwm set 20 16 byte 1 frame2 set 0 1 0 0 0 1 0 0 0 0 1 frame 2 pwm set 21 16 byte 2 frame3 set 0 1 0 0 0 1 0 0 0 1 0 frame 3 pwm set 22 16 byte 3 frame4 set 0 1 0 0 0 1 0 0 0 1 1 frame 4 pwm set 23 16 byte 4 anaset 0 1 0 0 0 1 1 0 0 1 0 analog set 32 3 byte 5 epctin 0 1 0 1 1 0 0 1 1 0 1 control eeprom cd 1 byte 6 epcout 0 1 0 1 1 0 0 1 1 0 0 cancel eeprom cc none 7 epmwr 0 1 0 1 1 1 1 1 1 0 0 write to eeprom fc none 8 epmrd 0 1 0 1 1 1 1 1 1 0 1 read from eeprom fd none 9 disctr2 0 1 0 1 1 1 1 0 0 1 1 display control_2 f3 1 byte 10 dispadj 0 1 0 1 1 1 1 1 0 1 0 display performance adjustment fa 1 byte 11 iipp 0 1 0 1 1 1 1 0 1 0 0 internal initialize preparation f4 1 byte 12
ST7636R ver 1.4 48/109 2006/09/06 8.2 ext=?0? function description (1) display on (dison) command: 1; parameter: none (afh) it is used to turn the display on. when the display is turned on, segment outputs and common outputs are generated at the level corresponding to the display data and display timing. you can?t turn on the display as long as the sleep mode is selected. thus, whenever using this command, you must cancel the sleep mode first. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 1 0 1 1 1 1 (2) display off (disoff) command: 1; parameter: none (aeh) it is used to forcibly turn the display off. as long as the display is turned off, every on segment and common outputs are forced to vss level. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 1 0 1 1 1 0 (3) normal display (disnor) comma nd: 1; parameter: none (a6h) it is used to normally highlight the display area without modifying contents of the display data ram. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 1 0 0 1 1 0 (4) inverse display (disinv) comma nd: 1; parameter: none (a7) it is used to inversely highlight the display area without modifying contents of the display data ram. this command does not invert non-display areas in case of using partial display. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 1 0 0 1 1 1 (5) common scan (comscan) command: 1; parameter: 1 (bbh) it is used to specify the common output direction in the pin of csel = l. this command helps increasing degrees of freedom of wiring on the lcd panel. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 0 1 1 1 0 1 1 ?e parameter1 (p1) 0 * * * * * p12 p11 p10 command scan direction when csel=0 configuration is selected, pins and common outputs are scanned in the order shown below. common scan direction p12 p11 p10 com0 pin com65 pin com66 pin com131 pin 0 0 0 0 0 1 0 1 0 0 1 1 0 ? 65 0 ? 65 65 ? 0 65 ? 0 66 ? 131 131 ? 66 66 ? 131 131 ? 66
ST7636R ver 1.4 49/109 2006/09/06 common scan direction original graphic : p12:p11:p10:0:0:0 (0 ? 65,66 ? 131) p12:p11:p10:0:0:1 (0 ? 65, 131 ? 66) p12:p11:p10:0:1:0 (65 ? 0, 66 ? 131) p12:p11:p10:0:1:1 (65 ? 0, 131 ? 66) figure 8.2.1 common scan direction configuration when csel=0 com0 com65 com131 com66 com0 com65 com131 com66 com0 com65 com66 com131 com65 com0 com131 com66 com65 com0 com66 com131
ST7636R ver 1.4 50/109 2006/09/06 figure 8.2.2 common scan direction configuration when csel=1 note : under csel=1 configuration, command # bbh will have no effect upon ic operation. the common scan direction is fixed. (6) display control_1 (disctr1) command: 1; parameter: 3 (cah) this command and succeeding parameters are used to perform the display timing-related setups. this command must be selected before using slpout. don?t change this command while the display is turned on. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 1 0 0 1 0 1 0 ?e parameter1(p1) 1 1 0 * * * p14 p13 p12 * * cl dividing ratio, f1 and f2 drive pattern. parameter2(p2) 1 1 0 * * p25 p24 p23 p22 p21 p20 drive duty parameter3(p3) 1 1 0 * * * p34 p33 p32 p31 p30 fr inverse-set value 1 (value 2 is in ext=?1? mode) p1: it is used to specify the cl dividing ratio. p14, p13, p12: cl dividing ratio. they are used to change number of dividing stages of external or internal clock. p14 p13 p12 cl dividing ratio 0 0 0 0 0 1 0 1 0 0 1 1 not divide 2 divisions 4 divisions 8 divisions p2: it is used to specify the duty of the module on block basis. duty * * p25 p24 p23 p22 p21 p20 (numbers of display lines)/4-1 example: 1/128 duty 0 0 0 1 1 1 1 1 128/4-1=31 this will output driving voltage waveforms from com0 to com127. . p3: it is used to specify the number of lines to be inversely highlighted on lcd panel from p34 to p30 (lines can be inversely highlighted in the range of 2 to 128 and p12 to p11 could be set in ext=?1? mode)
ST7636R ver 1.4 51/109 2006/09/06 define example ext=1 (command= f3h) ext=0 (command= cah) inversely highlighted line p12 p11 p10 p34 p33 p32 p31 p30 inversely highlighted lines-1 example: 0ah 0 0 0 0 1 0 1 0 11-1=10 example: 8ch 1 0 0 0 1 1 0 0 77-1=76 in the default, 0 inverse highlight lines are selected. p34=?0?: inversion occours every frame. p34=?1?: independent from frames. (7) sleep in/out preparation (slpp) command: 1; parameter: 1 (04h) using this command to setup ready status for sleep-in or sleep out. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 0 0 0 0 1 0 0 ?e parameter(p1) 1 1 0 0 0 1 1 1 1 1 p10 sleep in/out ready p10 =? 1?: ready for sleep in. p10 = ?0?: ready for sleep out. parameter 3fh is used to initialize sleep-in sequencing, an d parameter 3eh is used to initialize sleep-out sequencing. (8) sleep in (splin) command: 1; parameter: none (95h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 0 1 0 1 0 1 (9) sleep out (slpout) command: 1;parameter: none (94h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 0 1 0 1 0 0 (10) page address set (paset) command: 1; parameter: 2 (75h) when mpu makes access to the display data ram, this command and succeeding parameters are used to specify the page address area. as the addresses are incremented from t he start to the end page in the page-direction scan, the column address is incremented by 1 and the page address is returned to the start page. note: that the start and end page must be specified as a pair. also, the relation ?start page < end page? must be maintained. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 1 1 1 0 1 0 1 ?e parameter1(p1) 1 1 0 p17 p16 p15 p14 p13 p12 p11 p10 start page parameter2(p2) 1 1 0 p27 p26 p25 p24 p23 p22 p21 p20 end page
ST7636R ver 1.4 52/109 2006/09/06 (11) column address set (caset) command: 1; parameter: 2 (15h) when mpu makes access to the display data ram, this command and succeeding parameters are used to specify the column address area. as the addresses are incremented from t he start to the end column in the column-direction scan, the page address is incremented by 1 and the column address is returned to the start column. note: that the start and end column must be specified as a pair. also, the relation ?start column < end column? must be maintained. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 0 0 1 0 1 0 1 ?e parameter1(p1) 1 1 0 p17 p16 p15 p14 p13 p12 p11 p10 start address parameter2(p2) 1 1 0 p27 p26 p25 p24 p23 p22 p21 p20 end address (12) data control (datctl) command: 1;parameter: 3 (bch) this command and succeeding parameters are used to perf orm various setups needed when mpu operates display data stored on the built-in ram. a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 0 1 1 1 1 0 0 ?e parameter1(p1) 1 1 0 * * * * * p12 p11 p10 normal/inverse display of page / column address and address scan direction. parameter2(p2) 1 1 0 * * * * * * * p20 rgb arrangement parameter3(p3) 1 1 0 * * * * * p32 p31 p30 gray-scale setup p1: it is used to specify the normal or inverse display of the page / column address and also to specify the address scanning direction. p10: normal/inverse display of the page address. p10=0: normal and p10=1: inverse p11: normal/reverse turn of column address. p11=0: normal rotation and p11=1: reverse rotation. p12: address-scan direction. p12=0: in the colu mn direction and p12=1: in the page direction. page address and page-address scan direction p12=0 column direction p11=0 0 1 2 129 130 131 p11=1 131 130 129 2 1 0 p10=0 p10=1 0 131 1 130 2 129 129 2 130 1 131 0
ST7636R ver 1.4 53/109 2006/09/06 p12=1 page direction p11=0 0 1 2 129 130 131 p11=1 131 130 129 2 1 0 p10=0 p10=1 0 131 1 130 2 129 129 2 130 1 131 0 p2: rgb arrangement. this parameter allows you to change rgb arrangement of data which is going to be written into ram, and therefore causes the inverse rgb rotation of the segment output of ST7636R. you can fit rgb arrangement on the lcd panel according to this parameter setting. p20 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 ? seg395 0 r g b r g b r g ? b 1 b g r b g r b g ? r (a) command #bch, data #00h (b) command #bch, data #01h ST7636R ( bump side ) ST7636R ( bump side )
ST7636R ver 1.4 54/109 2006/09/06 (c) command #bch, data #02h (d) command #bch, data #03h figure 8.2.3 different ram accessing setup when csel=0 under command #bbh, data #00h (a) command #bch, data #00h (b) command #bch, data #01h (c) command #bch, data #02h (d) command #bch, data #03h (e) command #bch, data #04h (f) command #bch, data #05h ST7636R ( bump side ) ST7636R ( bump side ) ST7636R ( bump side ) ST7636R ( bump side )
ST7636R ver 1.4 55/109 2006/09/06 (g) command #bch, data #06h (h) command #bch, data #07h figure 8.2.3 different ram accessing setup when csel=0 under command #bbh, data #00h (continue) (e) command #bch, data #04h (f) command #bch, data #05h (g) command #bch, data #06h (h) command #bch, data #07h p3: gray scale setup. using this parameter, you can select the 4k, 65k, 262k, and 16m display mode depending on the difference in rgb data arrangement. p32 p31 p30 numbers of gray-scale 0 0 1 64-gray 65k 0 1 0 64-gray 262k 1 0 0 64-gray 16m 1 0 1 16-gray 4k type a 1 1 0 16-gray 4k type b (13) memory write (ramwr) command: 1; parameter: numbers of data written (5ch) when mpu writes data to the display memory, this command turns on the data entry mode. entering this command always sets the page and column address at the start address. you can rewrite contents of the display data ram by entering data succeeding to this command. at the same time, this operation increments the page or column address as applicable. the write mode is automatically cancelled if any other command is entered. ST7636R ( bump side ) ST7636R ( bump side )
ST7636R ver 1.4 56/109 2006/09/06 1. 8-bit bus a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 1 0 1 1 1 0 0 ?e parameter 1 1 0 data to be written data to be written 2. 16-bit bus a0 rd rw d15 d14 ? d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 * * ? * * 0 1 0 1 1 1 0 0 memory write parameter 1 1 0 data to be written write data (14) memory read (ramrd) command: 1; parameter: numbers of data read (5dh) when mpu read data from the display memory, this command turns on the data read mode. entering this command always sets the page and column address at the start address. after entering this command, you can read contents of the display data ram. at the same time, this operation increments the page or column address as applicable. the data read mode is automatically cancelled if any other command is entered. 1. 8-bit bus a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 1 0 1 1 1 0 1 ?e parameter 1 0 1 data to be read data to be read 2. 16-bit bus a0 rd rw d15 d14 ?. d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 * * * * * 0 1 0 1 1 1 0 1 memory read parameter 1 0 1 data to be read read data (15) partial in (ptlin) command: 1; parameter: 2 (a8h) this command and succeeding parameters specify the partial display area. this command is used to turn on partial display of the screen (dividing screen by lines) in order to save power. since ST7636R processes the liquid crystal display signal on 4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block basis). a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 0 1 0 1 0 0 0 ?e parameter(p1) 1 1 0 * * p15 p14 p13 p12 p11 p10 start block address parameter(p2) 1 1 0 * * p25 p24 p23 p22 p21 p20 end block address a block address that can be specified for the partial display must be the display one (don?t try to specify an address not to be displayed when scrolled). (16) partial out (ptlout) command: 1; parameter: 0 (a9h) this command is used to exit from the partial display mode. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 1 0 1 0 0 1
ST7636R ver 1.4 57/109 2006/09/06 (17) read modify write in (rmwin) command: 1; parameter: 0 (e0h) this command is used along with the column address set command, page address set command and read modify write out command. this function is used when frequently modifying data to specify a specific display area such as blinking cursor. first set a specific display area using the column and page address commands. then, enter this command to set the column and page addresses at the start address of the specific area. when this operation is complete, the column (page) address won?t be modified by the display data read command. it is incremented only when the display data write comm and is used. you can cancel this mode by entering the read modify write out or any other command. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 1 0 0 0 0 0 (18) read modify write out (rmwout) command: 1; parameter: 0 (eeh) enter this command cancels the read modify write mode a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 1 0 1 1 1 0 (19) area scroll set (ascset) command: 1; parameter: 4 (aah) it is used when scrolling only the specified portion of the screen (dividing the screen by lines). this command and succeeding parameters specify the type of area scroll, fix area and scroll area. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 0 1 0 1 0 1 0 ?e parameter(p1) 1 1 0 * * p15 p14 p13 p12 p11 p10 top block address parameter(p2) 1 1 0 * * p25 p24 p23 p22 p21 p20 bottom block address parameter(p3) 1 1 0 * * p35 p34 p33 p32 p31 p30 number of specified blocks parameter(p4) 1 1 0 * * * * * * p41 p40 area scroll mode p4: it is used to specify an area scroll mode. p41 p40 type of area scroll 0 0 0 1 1 0 1 1 center screen scroll top screen scroll bottom screen scroll whole screen scroll
ST7636R ver 1.4 58/109 2006/09/06 center screen scroll top screen scroll bottom screen scroll whole screen scroll fixed area scroll area since ST7636R processes the liquid crystal display signals on the four-line basis (block basis), fix and scroll areas are also specified on the four-line basis (block basis). ddram address corresponding to the top fix area is set in the block address incrementing direction starting with 0 block. ddram address corresponding to the bottom fix area is set in the block address decreasing direction starting with 32 st block. other ddram blocks excluding the top and bottom fix areas are assigned to the scroll + background areas. p1: it is used to specify the top block address of the scroll + background areas. specify the 0 th block for the top screen scroll or whole screen scroll. p2: it specifies the bottom address of the scroll+ background areas. specify the 32 th block for the bottom or whole screen scroll. required relation between the start and end blocks (top block address ST7636R ver 1.4 59/109 2006/09/06 p3 1 1 0 * * 0 1 1 1 1 0 number of specific blocks = 30 p4 1 1 0 * * * * * * 0 0 area scroll mode = center (20) scroll start address set (scstart) command:1 parameter: 1 (abh) this command and succeeding parameters are used to sp ecify the start block address of the scroll area. note: that you must execute this command after executing the area scroll set command. scroll becomes available by dynamically changing the start block address. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 0 1 0 1 0 1 1 ?e parameter(p1) 1 1 0 * * p15 p14 p13 p12 p11 p10 start block address (21) internal oscillation on (oscon) command: 1; parameter: 0 (d1h) this command turns on the internal oscillation circuit. it is valid only when the internal oscillation circuit of cls = high is used. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 0 1 0 0 0 1 (22) internal oscillation off (osoff) command: 1; parameter: 0 (d2h) it turns off the internal oscillation circuit. this circuit is turned off in the reset mode. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 0 1 0 0 1 0 (23) power control set (pwrctr) command: 1; parameter: 1 (20h) this command is used to turn on or off the booster circuit, follower voltage, and voltage regulator circuit. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 1 0 0 1 0 0 0 0 0 ?e parameter(p1) 1 1 0 * * * 0 p13 0 p11 p10 lcd drive power p10: it turns on or off the voltage regulator voltage. p10 = ?1?: on. p10 =? 0?: off p11: it turns on or off the follower circuit. p11 = ?1?: on. p11 =? 0?: off p13:it turns on or off the booster. p13 = ?1?: on. p13 =? 0?: off (24) electronic volume control (volctr) command: 1; parameter: 2 (81h) the command is used to program the optimum lcd supply voltage vop (v0) reference to 7.10.2 a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 0 0 0 0 0 0 1 ?e
ST7636R ver 1.4 60/109 2006/09/06 parameter(p1) 1 1 0 * * p15 p14 p13 p12 p11 p10 set vop[5:0] parameter(p2) 1 1 0 * * * * * p18 p17 p16 set vop[8:6] (25) increment electronic control (volup) command: 1; parameter: 0 (d6h) with the volup and voldown command the vop voltage and therewith the contrast of the lcd can be adjusted. this command increments electronic control value vop[5:0] of voltage regulator circuit by 1. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 0 1 0 1 1 0 if you set the electronic control value to 111111, the control value is set to 000000 after this command has been executed. (26) decrement electronic control (voldown) command: 1; parameter: 0 (d7h) with the volup and voldown command the vop voltage and therewith the contrast of the lcd can be adjusted. this command decrements electronic control value vop[5:0] of voltage regulator circuit by 1. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 0 1 0 1 1 1 if you set the electronic control value to 000000, the control value is set to 111111 after this command has been executed. table 8.1.1 possible vop[5:0] values electronic control value decimal equivalent vop offset 111111 31 +1240 mv 111110 30 +1200 mv 111101 29 +1160 mv ? ? ? 000010 2 +80 mv 000001 1 +40 mv 000000 0 0 mv 111111 -1 -40 mv 111110 -2 -80 mv ? ? ? 100010 -30 -1200 mv 100001 -31 -1240 mv 100000 -32 - 1280mv
ST7636R ver 1.4 61/109 2006/09/06 (27) status read (stread) command: 1; parameter: none it is the command for reading the internal condition of the ic. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 0 1 (8) status data issue stread (status read) command only to read the internal condition of the ic. one status data can be displayed depending on the setting. issue the nop command after the stread (status read) command. the status data will be composed of 8 bits below: d7: area scroll mode d6: area scroll mode d5: rmw on/off d4: scan direction d3: display on/off d2: eeprom access d1: display normal/inverse d0: partial display refer to p41 (ascset) refer to p40 (ascset) 0 : out 0 : column 0 : off 0: outaccess 0 : normal 0 : off 1 : in 1 : page 1 : on 1: inaccess 1 : inverse 1 : on (28) read register 1 (epsrrd1) command: 1; parameter: 0 (7ch) it is the command for reading the electronic control values. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 0 1 1 1 1 1 0 0 issue the epsrrd1 and then stread (status read) commands in succession to read the electronic control values. one status data can be displayed depending on the setting. also, always issue the nop command after the stread (status read) command. the status data will be composed of 8 bits below: d7: 0 d6: 0 d[5:0]: vop[5:0] refer to electronic volume control values vop[5:0] (29) read register 2 (epsrrd2) command: 1 ;parameter: 0 (7dh) it is the command for reading id codes of the ST7636R and the built-in resistance ratio. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 0 1 1 1 1 1 0 1 issue the epsrrd2 and then stread (status read) commands in succession to read ic?s id and the built-in resistance ratio. one status data can be displayed depending on the setting. also, always issue the nop command after the stread (status read) command. the status data will be composed of 8 bits below: d[7:3]: ST7636R id codes d[2:0]: vop[8:6] 00001 refer to the built-in resistance ratio vop[8:6]
ST7636R ver 1.4 62/109 2006/09/06 (30) non-operating (nop) command: 1; parameter: 0 (25h) this command does not affect the operation. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 0 0 1 0 0 1 0 1 this command, however, has the function of canceling the ic test mode. thus, it is recommended to enter it periodically to prevent malfunctioning due to noise and such. (31) eeprom function start (eeo k) command:1;parameter:1(07h) in the otp read/write flow, eeprom is ready after i ssuing this command. its parameter is set to 19h. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 0 0 0 0 1 1 1 ?e parameter(p1) 1 1 0 0 0 0 1 1 0 0 1 19h (32) reserved (82h) do not use this command. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 0 0 0 0 0 1 0 (33) auto-sampling (ausam) command: 1; parameter: none (60h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 0 1 1 0 0 0 0 0 8.3 ext=?1? function description (1) set frame1 value (frame1 set) command: 1; parameter: 16 (20h) command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function frame1 set 0 1 0 0 0 1 0 0 0 0 0 frame 1 pwm set a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function parameter1(p1) 1 1 0 * * * p14 p13 p12 p11 p10 set rgb level 0 of 1st frame parameter2(p2) 1 1 0 * * * p24 p23 p22 p21 p20 set rgb level 1 of 1st frame parameter15(p15) 1 1 0 * * * p154 p153 p152 p151 p150 set rgb level 14 of 1st frame parameter16(p16) 1 1 0 * * * p164 p163 p162 p161 p160 set rgb level 15 of 1st frame (2)set frame2 value (frame2 set) command: 1; parameter: 16 (21h) command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function
ST7636R ver 1.4 63/109 2006/09/06 frame2 set 0 1 0 0 0 1 0 0 0 0 1 frame 2 pwm set a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function parameter1(p1) 1 1 0 * * * p14 p13 p12 p11 p10 set rgb level 0 of 2nd frame parameter2(p2) 1 1 0 * * * p24 p23 p22 p21 p20 set rgb level 1 of 2nd frame parameter15(p15) 1 1 0 * * * p154 p153 p152 p151 p150 set rgb level 14 of 2nd frame parameter16(p16) 1 1 0 * * * p164 p163 p162 p161 p160 set rgb level 15 of 2nd frame (3) set frame3 value (frame3 set) command: 1; parameter: 16 (22h) command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function frame3 set 0 1 0 0 0 1 0 0 0 1 0 frame 3 pwm set a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function parameter1(p1) 1 1 0 * * * p14 p13 p12 p11 p10 set rgb level 0 of 3rd frame parameter2(p2) 1 1 0 * * * p24 p23 p22 p21 p20 set rgb level 1 of 3rd frame parameter15(p15) 1 1 0 * * * p154 p153 p152 p151 p150 set rgb level 14 of 3rd frame parameter16(p16) 1 1 0 * * * p164 p163 p162 p161 p160 set rgb level 15 of 3rd frame (4) set frame4 value (frame4 set) command: 1; parameter: 16 (23h) command a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function frame4 set 0 1 0 0 0 1 0 0 0 1 1 frame 4 pwm set a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function parameter1(p1) 1 1 0 * * * p14 p13 p12 p11 p10 set rgb level 0 of 4th frame parameter2(p2) 1 1 0 * * * p24 p23 p22 p21 p20 set rgb level 1 of 4th frame parameter15(p15) 1 1 0 * * * p154 p153 p152 p151 p150 set rgb level 14 of 4th frame parameter16(p16) 1 1 0 * * * p164 p163 p162 p161 p160 set rgb level 15 of 4th frame the default value of rgb level set fram1 set fram2 set fram3 set frame4 set rgb level0 00 00 00 00 rgb level1 02 02 02 02 rgb level2 05 05 05 05 rgb level3 07 07 07 08
ST7636R ver 1.4 64/109 2006/09/06 rgb level4 0a 0a 0a 0b rgb level5 0d 0d 0d 0c rgb level6 0f 10 0f 10 rgb level7 11 12 11 12 rgb level8 13 14 13 14 rgb level9 16 16 16 15 rgb level10 18 18 18 17 rgb level11 19 19 19 1a rgb level12 1b 1b 1b 1a rgb level13 1c 1c 1c 1d rgb level14 1d 1d 1d 1e rgb level15 1e 1e 1e 1e all the modulation range of each level for each frame is from 00?h to 1f?h. example ?g paint setup void loadpaint( void ) { write( command, 0x0031 ); // ext = 1 write( command, 0x0020 ); // palette frc1 setup write( data, 0x0000 ); // rgb level0 setup write( data, 0x0002 ); // rgb level1 setup write( data, 0x0005 ); // rgb level2 setup ??. ??. ??. ??. write( data, 0x001e ); // rgb level15 setup write( command, 0x0021 ); // palette frc2 setup write( data, 0x0000 ); // rgb level0 setup write( data, 0x0002 ); // rgb level1 setup write( data, 0x0005 ); // rgb level2 setup ??. ??. ??. ??. write( data, 0x001e ); // rgb level15 setup write( command, 0x0022 ); // palette frc3 setup write( data, 0x0000 ); // rgb level0 setup write( data, 0x0002 ); // rgb level1 setup write( data, 0x0005 ); // rgb level2 setup ??. ??. ??. ??. write( data, 0x001e ); // rgb level15 setup write( command, 0x0023 ); // palette frc4 setup write( data, 0x0000 ); // rgb level0 setup write( data, 0x0002 ); // rgb level1 setup write( data, 0x0005 ); // rgb level2 setup ??. ??. ??. ??.
ST7636R ver 1.4 65/109 2006/09/06 write( data, 0x001e ); // rgb level15 setup write( command, 0x0030 ); // ext = 0 } (5) analog set (anaset) command 1; parameter: 3 (32h) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 0 0 1 1 0 0 1 0 ?e parameter1(p1) 1 1 0 * * * * * p12 p11 p10 osc frequency adjustment parameter2(p2) 1 1 0 * * * * * * p21 p20 booster efficiency set parameter3(p3) 1 1 0 * * * * * p32 p31 p30 bias setting p1: osc frequency adjustment p12 p11 p10 cl pin frequency ( khz ) : cl dividing ratio setting = 00h (no division) cl pin frequency ( khz ) : cl dividing ratio setting = 04h (divided by 2) 0 0 0 10.46 5.23 0 0 1 10.82 5.41 0 1 0 11.67 5.84 0 1 1 12.74 6.37 1 0 0 14.03 7.02 1 0 1 15.63 7.82 1 1 0 17.61 8.81 1 1 1 20.32 10.16 osc frequency can be adjusted by p1 setting and command cah, see page 51. the default osc frequency (cl pin frequency) is 10.46 khz. and the frame frequency is from osc frequency and duty setting, as the formula shown below: frame frequency = osc frequency / (duty+1) example: 1. duty=132, p1 setting=[000], frame frequency=10.46khz/133~78.64hz 2. duty=128, p1 setting=[101], frame frequency=15.63khz/129~121.16hz p2: booster efficiency set p21 p20 frequency ( hz ) 0 0 level 1 0 1 level 2 1 0 level 3
ST7636R ver 1.4 66/109 2006/09/06 1 1 level 4 by booster stages (2x, 3x, 4x, 5x, 6x, 7x, 8x) and booster efficiency (level1~4) commands, we could easily set the best booster performance with suitable current consumption. if the boos ter efficiency is set to higher level (level4 is higher than level1). the boost efficiency is better than lower level, and it just need few more power consumption current. p3: select lcd bias ratio of the voltage required for driving the lcd. p32 p31 p30 lcd bias 0 0 0 1/12 0 0 1 1/11 0 1 0 1/10 0 1 1 1/9 1 0 0 1/8 1 0 1 1/7 1 1 0 1/6 1 1 1 1/5 (6) control eeprom: 1; parameter: 1 (cdh) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 0 0 1 1 0 1 parameter1(p1) 1 1 0 * * p15 * * * * * p15: when setting ?1? ? the write enable of eeprom will be opened. p15: when setting ?0? ? the read enable of eeprom will be opened. (7) cancel eeprom command: 1;parameter: none (cch) a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 0 0 1 1 0 0 (8) write data to eeprom (epmwr) co mmand: 1; parameter: none (fch) a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 1 1 1 1 0 0 (9) read data from eeprom (epmwr) co mmand: 1; parameter: none (fdh) a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 1 1 1 1 1 1 0 1 (10) display control_2 (disctr2) command: 1; parameter: 1 (f3h)
ST7636R ver 1.4 67/109 2006/09/06 this command is used to extend the higher byte of inversing lines highlighted on lcd panel from p12 to p10 and p33 to p30 (lines can be inversely highlighted in the range of 2 to 128) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 1 1 1 0 0 1 1 ?e parameter1(p1) 1 1 0 * * * * * p12 p11 p10 fr inverse-set value 2 define example ext=1 (command= f3h) ext=0 (command= cah) inversely highlighted line p12 p11 p10 p34 p33 p32 p31 p30 inversely highlighted lines-1 example: 0ah 0 0 0 0 1 0 1 0 11-1=10 example: 8ch 1 0 0 0 1 1 0 0 77-1=76 in the default, 0 inverse highlight lines are selected. p34=?0?: inversion occours every frame. p34=?1?: independent from frames. (11) display performance adjustment (dispadj) command: 1; parameter: 1 (fah) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 1 1 1 1 0 1 0 display performance adjustment parameter1(p1) 1 1 0 * * * p14 p13 p12 p11 p10 fine tuning level set ST7636R provide the function of 32 levels fine tuning to adjust best crosstalk performance for each module. just like vop offset for different modules, the fine tuning level value can also be stored in eeprom, and therefore each module can have its individual setup for best display performance. due to ic and module process variation, it?s hard for all modules to have same display performance. by using this command, different modules can adjust to the best performance by having different parameters of dispadj. when loading eeprom, this individual parameter can be loaded into ic and best display performance can be achieved. detail using method please refer ST7636R eeprom user manual guide. (12) internal initialize preparation (iipp) command: 1; parameter: 1 (f4h) use this command to set internal initializing for ready status. a0 rd rw d7 d6 d5 d4 d3 d2 d1 d0 function command 0 1 0 1 1 1 1 0 1 0 0 ?e parameter(p1) 1 1 0 0 1 0 1 1 0 0 0 internal initialize sequencing 8.4 ext=?0? or ?1? function description (1) extension instruction disable (ext in ) command:1 parameter: none (30h) use the ?ext=0? command table
ST7636R ver 1.4 68/109 2006/09/06 a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 0 0 1 1 0 0 0 0 (2) extension instruction enable (ext out) command:1 parameter: none (31h) use the extended command table (ext=?1?) a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 command 0 1 0 0 0 1 1 0 0 0 1
ST7636R ver 1.4 69/109 2006/09/06 8.5 referential instruction setup flow 8.5.1 initializing with the built-in power supply circuits figure 8.5.1.1 initializing with the built-in power supply circuits
ST7636R ver 1.4 70/109 2006/09/06 example ?g initial code for 128x128 void ST7636R_init( void ) { write( command, 0x30 ); // ext = 0 write( command, 0x04 ); // sleep in/out preparation write( data, 0x3e ); // sleep in/out sequencing write( command, 0x31 ); // ext = 1 write( command, 0xf4 ); // in ternal initialize preparation write( data, 0x58 ); // internal initialize sequencing write( command, 0x30 ); // ext = 0 write( command, 0x94 ); // sleep out write( command, 0xd1 ); // internal osc on write( command, 0xca ); // display control write( data, 0x00 ); // cl divisions ratio write( data, 0x1f ); // duty setting (= 128) write( data, 0x00 ); // n-line inverse-set value write( command, 0x31 ); // ext = 1 write( command, 0x32 ); // analog setting write( data, 0x00 ); // osc freqency adjustment write( data, 0x01 ); // booster efficiency setting write( data, 0x00 ); // bias setting (=1/12) write( command, 0x30 ); // ext = 0 write( command, 0x81 ); // electronic volume control write( data, 0x1b ); // ev:vop[5:0]_6bit write( data, 0x04 ); // ev:vop[8:6]_3bit // vop is 14.92v under this condition for example write( command, 0x20 ); // power control write( data, 0x0b ); // b/f/r = on/on/on write( command, 0x30 ); // ext = 0 write( command, 0x60 ); // auto-sampling delay(50000); // delay 50ms loadeeprom(); // load eeprom (refer page 71) loadpaint(); // load gamma table parameter (refer page 64) write( command, 0x30 ); // ext = 0 write( command, 0xa7 ); // inverse display write( command, 0xbb ); // com scan direction write( data, 0x01 ); // 0~65 / 131~66 write( command, 0xbc ); // data scan direction write( data, 0x00 ); // page / column address setting write( data, 0x00 ); // rgb arrangement (0:rgb 1:bgr) write( data, 0x01 ); // gray-scale setup ( 64-gray: 01h) write( command, 0x75 ); // page address set write( data, 0x00 ); // from page address 0 write( data, 0x7f ); // to page address 127 write( command, 0x15 ); // column address set write( data, 0x00 ); // from column address 0 write( data, 0x7f ); // to column address 127 write( command, 0xaf ); // display on write( command, 0x30 ); // ext = 0
ST7636R ver 1.4 71/109 2006/09/06 } example ?g load eeprom void loadeeprom( void ) { write( command, 0x31 ); // ext = 1 write( command, 0xcd ); // enable eeprom write( data, 0x00 ); // delay(50000); // delay 50ms write( command, 0xfd ); // load eeprom delay(50000); // delay 50ms write( command, 0xcc ); // disable eeprom write( command, 0x30 ); // ext = 0 } 8.5.2 data displaying normal state display data ram addressing by instruction [data control: bch] [set page address: 75h] [set column address: 15h] [entry memory write mode: 5ch] display data write [display data write] end of data display yes no end of display data write ? figure 8.5.2.1 data displaying
ST7636R ver 1.4 72/109 2006/09/06 example ?g display for 128x128 void display( char *pattern ) { unsigned char i, j; write( command, 0x30 ); // ext = 0 write( command, 0x15 ); // column address set write( data, 0 ); // from column address 0 to 127 write( data, 127 ); write( command, 0x75 ); // page address set write( data, 0 ); // from page address 0 to 127 write( data, 127 ); write( command, 0x5c ) // entry memory write mode for( j = 0; j < 127 ; j++ ) for( i = 0 ; i < 127 ; i++ ) write( data, pattern[j*128+i] ); // display data write } 8.5.3 partial display in/out figure 8.5.3.1 partial display in/out
ST7636R ver 1.4 73/109 2006/09/06 example ?g partial display in operation void partailin( unsigned char start_block, unsigned char end_block ) { write( command, 0x30 ); // ext = 0 write( command, 0xa8); // partial display in function write( data, start_block ); // start block write( data, end_block ); // end block } void partailout( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xa9 ); // partial display out function } extern unsigned char *display_pattern; void main() { partialin( 11, 18 ); // entry partial display mode windowing( 0, 11*4, 131, 18*4 ); // set the page and column range partialdisplay( display_pattern ); // fill the data into partial display area . . . partialout(); // out of partial display mode }
ST7636R ver 1.4 74/109 2006/09/06 8.5.4 scroll display figure 8.5.4.1 scroll display example ?g screen scroll operation void centerscreenscroll( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xaa); // partial display in function write( data, 0x0a ); // top_block=10 write( data, 0x14 ); // bottom_block=20 write( data, 0x14 ); // number of specified blocks=bottom_block=20 write( data, 0x00 ); // area scroll type=center screen scroll scrollup() or scrolldown(); // scroll up or scroll down }
ST7636R ver 1.4 75/109 2006/09/06 void topscreenscroll( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xaa); // partial display in function write( data, 0x00 ); // top_block=0 write( data, 0x14 ); // bottom_block=20 write( data, 0x14 ); // number of specified blocks=bottom_block=20 write( data, 0x01 ); // area scroll type=top screen scroll scrollup() or scrolldown(); // scroll up or scroll down } void bottomscreenscroll( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xaa); // partial display in function write( data, 0x0a ); // top_block=10 write( data, 0x20 ); // bottom_block=32 write( data, 0x20 ); // number of specified blocks=bottom_block=32 write( data, 0x02 ); // area scroll type=bottom screen scroll scrollup() or scrolldown(); // scroll up or scroll down } void wholescreenscroll( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xaa); // partial display in function write( data, 0x00 ); // top_block=0 write( data, 0x20 ); // bottom_block=32 write( data, 0x20 ); // number of specified blocks=bottom_block=32 write( data, 0x03 ); // area scroll type=whole screen scroll scrollup() or scrolldown(); // scroll up or scroll down } void scrollup( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xab); // scroll start set write( data, top_block); // start block address=top_block delay(); // delay write( command, 0x00ab); // scroll start set write( data, top_block +1 ); // start block address= top_block+1 delay(); // delay write( command, 0x00ab); // scroll start set write( data, top_block +2 ); // start block address= top_block +2 delay(); // delay ??
ST7636R ver 1.4 76/109 2006/09/06 ?? write( command, 0x00ab); // scroll start set write( data, bottom_block ); // start block address= bottom_block delay(); // delay } void scrolldown( void ) { write( command, 0x30 ); // ext = 0 write( command, 0x00ab); // scroll start set write( data, bottom_block); // st art block address= bottom_block delay(); // delay write( command, 0x00ab); // scroll start set write( data, bottom_block -1 ); // start block address= bottom_block -1 delay(); // delay write( command, 0x00ab); // scroll start set write( data, bottom_block -2 ); // start block address= bottom_block -2 delay(); // delay ?? ?? write( command, 0x00ab); // scroll start set write( data, top _block ); // start block address= top_block delay(); // delay } 8.5.5 read-modify-write cycle
ST7636R ver 1.4 77/109 2006/09/06 figure 8.5.5.1 read-write-modify cycle example ?g read-write-modify cycle void readmodifywritein( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xe0 ); // entry the read-modify-write mode } void readmodifywriteout( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xee ); // out of partial display mode } extern unsigned char *display_pattern; void main() { unsigned pixel, i; windowing( 11, 31, 80, 50 ); // set the page and column range readmodifywritein(); // entry the read-modify-write mode
ST7636R ver 1.4 78/109 2006/09/06 for( i = 0 ; i < 1400 ; i++ ) { read( data ); // for dummy read pixel = read( data ); // pixel read pixel = pixel & 0x07ff; // pixel modify: red filter write( data, pixel ); } readmodifywriteout(); // out of read-modify-write mode } 8.5.6 power off power off execute the ?sleep in flow? power off (vdd-vss) normal state end of power off keeping /res pin =?l? internal state t r /res normal state vdd reset t r > 12 ms power off keep the /res = low figure 8.5.6.1 power off 8.5.7 sleep in/out
ST7636R ver 1.4 79/109 2006/09/06 fig 8.5.7.1 sleep in/out flow example ?g sleep in operation void sleepin( void ) { write( command, 0x30 ); // ext = 0 write( command, 0xae ); // display off write( command, 0x20); // power control write( data, 0x03 ); // b/f/r = off/on/on write( command, 0x04 ); // sleep in preparation write( data, 0x3f ); // sleep in sequencing delay( 500ms); // delay 500ms write( command, 0x95 ); // sleep in } example ?g sleep out operation void sleepout( void ) { write( command, 0x30 ); // ext = 0 write( command, 0x04 ); // sleep out preparation write( data, 0x3e ); // sleep out sequencing write( command, 0x20 ); // power control write( data, 0x0b ); // b/f/r = on/on/on write( command, 0x94 ); // sleep out delay( 100ms ); // delay 100ms write( command, 0xaf ); // display on } 9. limiting values normal state [set sleep in by instruction: 95h] sleep in sequencing : [display off: aeh] [booster off only: 20h^03h] [set sleep in preparation: 04h^3fh] delay 500ms start of sleep in end of sleep in sleep in status [set sleep out by instruction: 94h] sleep out sequencing : [set sleep out preparation: 04h^3eh] [set analog power control: 20h^0bh] start of sleep out delay 100ms [display on: afh] end of sleep out
ST7636R ver 1.4 80/109 2006/09/06 in accordance with the absolute maximum rating system; see notes 1 and 2. parameter symbol conditions unit power supply voltage vdd, vdd1~vdd5 ?0.5 ~ +3.6 v power supply voltage vlcd in ?0.5 ~ +20 v power supply voltage v1, v2, v3, v4 0.3 to vlcd in v input voltage vin ?0.5 to vdd+0.5 v output voltage vo ?0.5 to vdd+0.5 v operating temperature (die) topr ?30 to +85 c storage temperature (die) tstr ?40 to +125 c system (mpu) side ST7636R chip side v lcd v ss v 1 to v 4 v ss v dd v ss v dd notes 1. stresses above those listed under limiting values may cause permanent damage to the device. 2. parameters are valid over operating temperature range unl ess otherwise specified. all voltages are with respect to v ss unless otherwise noted. 3. insure that the voltage levels of v1, v2, v3, and v4 are always such as below: vlcd in ? v0 ? v1 ? v2 ? v3 ? v4 ? vss, v4 < 2.3v
ST7636R ver 1.4 81/109 2006/09/06 10. handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see ?handling mos devices?). 11. dc characteristics v dd = 1.8 v to 3.3v (vdd, vdd1), v dd = 2.4 v to 3.3v (vdd2, vdd3, vdd4, vdd5) ; v ss = 0 v; v lcd = 3.76 to 18.0v; t amb = -30 j to +85 j ; unless otherwise specified . rating item symbol condition min. typ. max. units applicable pin high-level input voltage vihc 0.7 x vdd ? vdd v *1 low-level input voltage vilc vss ? 0.3 x vdd v *1 high-level output voltage vohc 0.7 x vdd ? vdd v *2 low-level output voltage volc vss ? 0.3 x vdd v *2 input leakage current ili vin = vdd or vss -1.0 ? 1.0 a *3 output leakage current ilo vin = vdd or vss -3.0 ? 3.0 a *4 liquid crystal driver on resistance ron ta = 25c (relative to vss) v0 in =14.7 v ? 1 10 k ? segn comn *5 internal oscillator fosc ? 10.42 20.83 khz *6 external input fcl ? 323.02 645.73 khz osc oscillator frequency frame frequency fframe 1/132 duty ta = 25c 31 pwm internal osc: fframe = fosc /(duty+1) external osc: fframe = fcl /[31*(duty+1)] hz rating item symbol condition min. typ. max. units applicable pin operating voltage (1) vdd vdd1 (relative to vss) 1.8 ? 3.3 v vss*7 operating voltage (2) vdd2 vdd3 vdd4 vdd5 (relative to vss) 2.4 ? 3.3 v vss internal power supply step-up output voltage circuit vlcd out (relative to vss) ? ? 20 v vlcd out
ST7636R ver 1.4 82/109 2006/09/06 voltage regulator circuit operating voltage vlcd in (relative to vss) ? ? 20 v vlcd in dynamic consumption current: during display, with the internal power supply off current consumed by total ics when an external power supply is used. rating test pattern symbol condition min. typ. max. units notes display pattern normal iss vdd = 2.8 v, booster x 7 v0 ? vss (vop) = 13.84 v @ 1/12 bias,1/132 duty ? 500 ? a *8 power down iss ta = 25c ? ? 10 a die notes to the dc characteristics 1. the maximum possible vlcd voltage that may be generated is depend on voltage, temperature, loading (display pattern), and internal clock rate. 2. power-down mode is meaning that during power down state, all static currents are switched off. 3. if external vlcd, the display load current is not transmitted to i dd . 4. external vlcd voltage is applied to vlcd in pin; vlcd in is disconnected from vlcd out . references for items market with * *1 the a0, d0 to d5, d6 (si), d7 (scl), /rd (e), /wr ,/(r/w), /cs, im s, osc, p/s, /dof, resb terminals. *2 the d0 to d7. *3 the a0,/rd (e), /wr ,/(r/w), /cs, and res terminals. *4 applies when the d0 to d5, d6 (si), d7 (scl) terminals are in a high impedance state. *5 these are the resistance values for when a 0.2 x v0 voltage is applied between the output terminal segn or comn and the various power supply terminals (v1, v2, v3, and v4). these are specified for the operating voltage range. ron = 0.2 v0/ ? i (where ? i is the current that flows when 0.2 v0 is applied while the power supply is on.) *6 the relationship between the oscillator frequency and the frame rate frequency under cl dividing ratio setting = 00h. *7 while a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the mpu is being accessed. *8 it indicates the current consumed on ics alone when the internal oscillator circuit and display are turned on.
ST7636R ver 1.4 83/109 2006/09/06 12. timing characteristics system bus read/write characteristics 1 (for the 8080 series mpu) t ah8 t aw8 t cyc8 t cclr ,t cclw t cchr ,t cchw t ds8 t acc8 t oh8 t dh8 /cs wr,rd a0 d0 to d7 (write) d0 to d7 (read) t as8 figure 12.1 (v dd =3.3v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units address hold time tah8 10 ? address setup time tas8 40 ? address setup time a0 taw8 0 ? system cycle time (write) tcyc8 170 ? ns /wr l pulse width (write) tcclw 50 ? /wr h pulse width (write) wr tcchw 130 ? system cycle time (read) tcyc8 160 ? /rd l pulse width (read) tcclr 80 ? /rd h pulse width (read) rd tcchr 80 ? write data setup time tds8 50 ? write data hold time tdh8 10 ? read access time tacc8 cl = 100 pf ? 70 read output disable time d0 to d7 toh8 cl = 100 pf ? 60 ns
ST7636R ver 1.4 84/109 2006/09/06 (v dd =2.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units address hold time tah8 10 ? address setup time tas8 50 ? address setup time a0 taw8 0 ? system cycle time (write) tcyc8 180 ? ns /wr l pulse width (write) tcclw 55 ? /wr h pulse width (write) wr tcchw 140 ? system cycle time (read) tcyc8 180 ? /rd l pulse width (read) tcclr 90 ? /rd h pulse width (read) rd tcchr 90 ? write data setup time tds8 55 ? write data hold time tdh8 10 ? read access time tacc8 cl = 100 pf ? 75 read output disable time d0 to d7 toh8 cl = 100 pf ? 65 ns (v dd =1.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units address hold time tah8 10 ? address setup time tas8 80 ? address setup time a0 taw8 0 ? system cycle time (write) tcyc8 400 ? ns /wr l pulse width (write) tcclw 70 ? /wr h pulse width (write) wr tcchw 300 ? system cycle time (read) tcyc8 400 ? /rd l pulse width (read) tcclr 200 ? /rd h pulse width (read) rd tcchr 200 ? write data setup time tds8 90 ? write data hold time tdh8 10 ? read access time tacc8 cl = 100 pf ? 90 read output disable time d0 to d7 toh8 cl = 100 pf ? 80 ns *1 the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. when the system cycle time is extremely fas t, (tr +tf) ?? (tcyc8 ? tcclw ? tcchw) for (tr + tf) ?? (tcyc8 ? tcclr ? tcchr) are specified. *2 all timing is specified using 20% and 80% of vdd as the reference. *3 tcclw and tcclr are specified as the overlap between /cs being ?l? and wr and rd being at the ?l? level.
ST7636R ver 1.4 85/109 2006/09/06 system bus read/write characteristics 1 (for the 6800 series mpu) t ah6 t aw6 t cyc6 t cclr ,t cclw t cchr ,t cchw t ds6 t acc6 t oh6 t dh6 cs1 (cs2="1") e a0 r/w d0 to d7 (write) d0 to d7 (read) t as6 figure 12.2 (v dd =3.3v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units address hold time tah6 10 ? address setup time tas6 50 ? address setup time a0 taw6 0 ? system cycle time (write) tcyc6 170 ? ns enable l pulse width (write) tcclw 130 ? enable h pulse width (write) wr tcchw 40 ? system cycle time (read) tcyc6 160 ? enable l pulse width (read) tcclr 80 ? enable h pulse width (read) rd tcchr 80 ? write data setup time tds6 50 ? write data hold time tdh6 10 ? read access time tacc6 cl = 100 pf ? 70 read output disable time d0 to d7 toh6 cl = 100 pf ? 60 ns
ST7636R ver 1.4 86/109 2006/09/06 (v dd =2.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units address hold time tah6 10 ? address setup time tas6 60 ? address setup time a0 taw6 0 ? system cycle time (write) tcyc6 195 ? ns enable l pulse width (write) tcclw 160 ? enable h pulse width (write) wr tcchw 45 ? system cycle time (read) tcyc6 180 ? enable l pulse width (read) tcclr 90 ? enable h pulse width (read) rd tcchr 90 ? write data setup time tds6 55 ? write data hold time tdh6 10 ? read access time tacc6 cl = 100 pf ? 75 read output disable time d0 to d7 toh6 cl = 100 pf ? 65 ns (v dd =1.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units address hold time tah6 10 ? address setup time tas6 100 ? address setup time a0 taw6 0 ? system cycle time (write) tcyc6 390 ? ns enable l pulse width (write) tcclw 300 ? enable h pulse width (write) wr tcchw 60 ? system cycle time (read) tcyc6 400 ? enable l pulse width (read) tcclr 200 ? enable h pulse width (read) rd tcchr 200 ? write data setup time tds6 90 ? write data hold time tdh6 10 ? read access time tacc6 cl = 100 pf ? 90 read output disable time d0 to d7 toh6 cl = 100 pf ? 80 ns *1 the input signal rise time and fall time (tr, tf) is specified at 15 ns or less. when the system cycle time is extremely fas t, (tr +tf) ?? (tcyc6 ? tewlw ? tewhw) for (tr + tf) ?? (tcyc6 ? tewlr ? tewhr) are specified. *2 all timing is specified using 20% and 80% of vdd as the reference. *3 tewlw and tewlr are specified as the overlap between /cs being ?l? and e.
ST7636R ver 1.4 87/109 2006/09/06 serial interface characteristics (for 4-line interface) t csh /cs1 (cs2="1") a0 si scl t ccss t sas t sah t scyc t slw t shw t sdh t sds t f t r fig 12.3 (v dd =3.3v,ta= ?30c to 85c, die) rating item signal symbol condition min. max. units serial clock period tscyc 80 ? ns scl ?h? pulse width tshw 40 ? scl ?l? pulse width scl tslw 40 ? address setup time tsas 10 ? address hold time a0 tsah 30 ? data setup time tsds 10 ? data hold time si tsdh 30 ? cs-scl time tcss 10 ? cs-scl time /cs tcsh 30 ? ns
ST7636R ver 1.4 88/109 2006/09/06 (v dd =2.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units serial clock period tscyc 90 ? ns scl ?h? pulse width tshw 45 ? scl ?l? pulse width scl tslw 45 ? address setup time tsas 10 ? address hold time a0 tsah 35 ? data setup time tsds 10 ? data hold time si tsdh 35 ? cs-scl time tcss 10 ? cs-scl time /cs tcsh 35 ? ns (v dd =1.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units serial clock period tscyc 100 ? ns scl ?h? pulse width tshw 50 ? scl ?l? pulse width scl tslw 50 ? address setup time tsas 10 ? address hold time a0 tsah 40 ? data setup time tsds 10 ? data hold time si tsdh 40 ? cs-scl time tcss 10 ? cs-scl time /cs tcsh 40 ? ns *1 the input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 all timing is specified using 20% and 80% of vdd as the standard.
ST7636R ver 1.4 89/109 2006/09/06 serial interface characteristics (for 3-line interface) fig 12.4 (v dd =3.3v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units serial clock period tscyc 80 ? ns scl ?h? pulse width tshw 40 ? scl ?l? pulse width scl tslw 40 ? data setup time tsds 10 ? data hold time si tsdh 30 ? cs-scl time tcss 10 ? cs-scl time /cs tcsh 30 ? ns t csh /cs1 (cs2="1") si scl t ccss t scyc t slw t shw t sdh t sds t f t r
ST7636R ver 1.4 90/109 2006/09/06 (v dd =2.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units serial clock period tscyc 90 ? ns scl ?h? pulse width tshw 45 ? scl ?l? pulse width scl tslw 45 ? data setup time tsds 10 ? data hold time si tsdh 35 ? cs-scl time tcss 10 ? cs-scl time /cs tcsh 35 ? ns (v dd =1.8v, ta= ?30c to 85c, die) rating item signal symbol condition min. max. units serial clock period tscyc 100 ? ns scl ?h? pulse width tshw 50 ? scl ?l? pulse width scl tslw 50 ? data setup time tsds 10 ? data hold time si tsdh 40 ? cs-scl time tcss 10 ? cs-scl time /cs tcsh 40 ? ns *1 the input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 all timing is specified using 20% and 80% of vdd as the standard.
ST7636R ver 1.4 91/109 2006/09/06 13. reset timing internal status t rw t r during reset reset complete /res fig 13.1 (vdd = 3.3v, ta = ?30c to 85c, die) rating item signal symbol condition min. typ. max. units reset time tr 900 ? ? ns reset ?l? pulse width resb trw 1200 ? ? ns (vdd = 2.8v, ta = ?30c to 85c, die) rating item signal symbol condition min. typ. max. units reset time tr 860 ? ? ns reset ?l? pulse width resb trw 1300 ? ? ns (vdd = 1.8v, ta = ?30c to 85c, die) rating item signal symbol condition min. typ. max. units reset time tr 690 ? ? ns reset ?l? pulse width resb trw 2040 ? ? ns
ST7636R ver 1.4 92/109 2006/09/06 14. display application examples between ST7636R and panel 14.1 128 x 128 panel and csel=0 configuration figure 14.1 128 x 128 panel and csel=0 configuration initialize setting ?g application suggestion register setting: command parameter description vdd, vdd1 = 1.8 ~ 3.3 ( v ) bbh p1 = 01h common scan direction vdd2 ~ vdd5 = 2.4 ~ 3.3 ( v ) cah p2 = 31h duty = 128 bias = 1 / 12 75h p1 = 0, p2 = 127 page = 0 ~ 127 duty = 128 15h p1 = 0, p2 = 127 column = 0 ~ 127 bch p1 = 00h address scan direction option pin setting: bch p2 = 00h rgb arrangement csel = 0 9. display application examples between
ST7636R ver 1.4 93/109 2006/09/06 14.2 128 x 128 panel and csel=0 configuration figure 14.2 128 x 128 panel and csel=0 configuration initialize setting ?g application suggestion register setting: command parameter description vdd, vdd1 = 1.8 ~ 3.3 ( v ) bbh p1 = 01h common scan direction vdd2 ~ vdd5 = 2.4 ~ 3.6 ( v ) cah p2 = 31h duty = 128 bias = 1 / 12 75h p1 = 0, p2 = 127 page = 0 ~ 127 duty = 128 15h p1 = 4, p2 = 131 column = 4 ~ 131 bch p1 = 02h address scan direction option pin setting: bch p2 = 01h rgb arrangement csel = 0
ST7636R ver 1.4 94/109 2006/09/06 14.3 128 x 128 panel and csel=1 configuration figure 14.3 128 x 128 panel and csel=1 configuration initialize setting ?g application suggestion register setting: command parameter description vdd, vdd1 = 1.8 ~ 3.3 ( v ) cah p2 = 31h duty = 128 vdd2 ~ vdd5 = 2.4 ~ 3.6 ( v ) 75h p1 = 0, p2 = 127 page = 0 ~ 127 bias = 1/12 15h p1 = 0, p2 = 127 column = 0 ~ 127 duty = 128 bch p1 = 00h address scan direction bch p2 = 00h rgb arrangement option pin setting: csel = 1
ST7636R ver 1.4 95/109 2006/09/06 14.4 128 x 128 panel and csel=1 configuration figure 14.4 128 x 128 panel and csel=1 configuration initialize setting ?g application suggestion register setting: command parameter description vdd, vdd1 = 1.8 ~ 3.3 ( v ) cah p2 = 31h duty = 128 vdd2 ~ vdd5 = 2.4 ~ 3.6 ( v ) 75h p1 = 0, p2 = 127 page = 0 ~ 127 bias = 1/12 15h p1 = 0, p2 = 127 column = 0 ~ 127 duty = 128 bch p1 = 03h address scan direction bch p2 = 00h rgb arrangement option pin setting: csel = 1
ST7636R ver 1.4 96/109 2006/09/06 15. the mpu interface (reference examples) the ST7636R series can be connected to either 8080 series mpus or to 6800 series mpus. moreover, using the serial interface it is possible to operate the ST7636R series chips with fewer signal lines. the display area can be enlarged by using multiple ST7636R series chips. when this is done, the chip select signal can be used to select the individual ics to access. (1) 8080 series mpus a0 do to d7 rd wr res v cc gnd mpu a0 cs1 d0 to d7 /rd (e) /wr (r/w) /res v dd v ss ST7636R reset v dd v ss cs1 if1 if2 if3 (2) 6800 series mpus a0 do to d7 rd wr res v cc gnd mpu a0 d0 to d7 e(/rd) r/w (/wr) /res v dd v ss ST7636R cs1 reset v dd v ss cs1 if1 if2 if3 (3) using the serial interface (4-line interface) a0 port 1 port 2 res v cc gnd a0 cs1 si scl /res v dd v ss reset v dd v ss mpu ST7636R cs1 if1 if2 if3
ST7636R ver 1.4 97/109 2006/09/06 (4) using the serial interface (3-line interface) port 1 port 2 res v cc gnd cs1 si scl /res v dd v ss reset v dd or v ss v ss mpu st7636 cs1 if1 if2 if3
ST7636R ver 1.4 98/109 2006/09/06 application circuits ( a ) 80 series 16-bit parallel interface: interface: 80 series 16-bit interface booster: 7x use internal resistors capacitor: 1.0 uf
ST7636R ver 1.4 99/109 2006/09/06 application circuits (continue) ( b ) 80 series 8-bit parallel interface: interface: 80 series 8-bit interface booster: 7x use internal resistors capacitor: 1.0 uf / 25v
ST7636R ver 1.4 100/109 2006/09/06 application circuits (continue) ( c ) 68 series 16-bit parallel interface ( with external power supply to vlcd ) : interface: 68 series 16-bit interface booster: register vc = 0 use external power supply to vlcd capacitor: 1.0 uf / 25v
ST7636R ver 1.4 101/109 2006/09/06 application circuits (continue) ( d ) 3 line serial peripheral interface: interface: 3 line serial peripheral interface booster: 7x use internal resistors capacitor: 1.0 uf / 25v
ST7636R ver 1.4 102/109 2006/09/06 application circuits (continue) ( e ) 4 line serial peripheral interface: interface: 4 line serial peripheral interface booster: 7x use internal resistors capacitor: 1.0 uf / 25v
ST7636R ver 1.4 103/109 2006/09/06 16. application note of vlcd and vop (v0) ito layout when using internal vo ltage generator, vlcd in ?b vlcd out must be connected together. v0 in and v0 out must be connected together too. in the following is the ito layout for vlcd in ?b vlcd out ?b v0 in and v0 out individually. please follow the way as below for these two lcd power voltages.
ST7636R ver 1.4 104/109 2006/09/06 17. application note of vdd and vss ito layout in the following is the ito layout of power system (vdd and vss). please follow the way as below for vdd and vss ito layout.
ST7636R ver 1.4 105/109 2006/09/06 18. application note of eeprom flow in the following is eeprom flow chart and its detail application programs. z eeprom flow chart b ?g adjust vop offset c ?g write eeprom check if write successfull y ? ng ok finish reset eeprom operation a ?g initial flow reset show test pattern a ?g initial flow load eeprom write( command , 0x31); write( command , 0xf4); write( data , 0x58); internal initialize when booster x6: vdd2~vdd5 =3.3v when booster x7: vdd2~vdd5 =2.8v~3.0v and booster: on , regulator: off , follower: off , dis p la y off internal initialize write( command , 0x31); write( command , 0xf4); write( data , 0x58); show test pattern
ST7636R ver 1.4 106/109 2006/09/06 z application programs a. initial flow void ST7636R_init( void ) { write( command, 0x30 ); // ext = 0 write( command, 0x04 ); // sleep in/out preparation write( data, 0x3e ); // sleep in/out sequencing write( command, 0x31 ); // ext = 1 write( command, 0xf4 ); // in ternal initialize preparation write( data, 0x58 ); // internal initialize sequencing write( command, 0x30 ); // ext = 0 write( command, 0x94 ); // sleep out write( command, 0xd1 ); // internal osc on write( command, 0xca ); // display control write( data, 0x00 ); // cl divisions ratio write( data, 0x1f ); // duty setting (= 128) write( data, 0x00 ); // n-line inverse-set value write( command, 0x31 ); // ext = 1 write( command, 0x32 ); // analog setting write( data, 0x00 ); // osc freqency adjustment write( data, 0x01 ); // booster efficiency setting write( data, 0x00 ); // bias setting (=1/12) write( command, 0x30 ); // ext = 0 write( command, 0x81 ); // electronic volume control write( data, 0x1b ); // ev:vop[5:0]_6bit write( data, 0x04 ); // ev:vop[8:6]_3bit // vop is 14.92v under this condition for example write( command, 0x20 ); // power control write( data, 0x0b ); // b/f/r = on/on/on write( command, 0x30 ); // ext = 0 write( command, 0x60 ); // auto-sampling delay(50000); // delay 50ms loadeeprom(); // load eeprom (refer page 71) loadpaint(); // load gamma table parameter (refer page 64) write( command, 0x30 ); // ext = 0 write( command, 0xa7 ); // inverse display write( command, 0xbb ); // com scan direction write( data, 0x01 ); // 0~65 / 131~66 write( command, 0xbc ); // data scan direction write( data, 0x00 ); // page / column address setting write( data, 0x00 ); // rgb arrangement (0:rgb 1:bgr) write( data, 0x01 ); // gray-scale setup ( 64-gray: 01h) write( command, 0x75 ); // page address set write( data, 0x00 ); // from page address 0 write( data, 0x7f ); // to page address 127 write( command, 0x15 ); // column address set write( data, 0x00 ); // from column address 0
ST7636R ver 1.4 107/109 2006/09/06 write( data, 0x7f ); // to column address 127 write( command, 0xaf ); // display on write( command, 0x30 ); // ext = 0 } b. adjust vop offset void adj_vop_offset(void) { int i,j=1; while(j) { if (keyscan1==0)i=1; // define keyscan1 for ?d6? use if (keyscan2==0)i=2; // define keyscan2 for ?d7? use if (keyscan3==0)i=3; // define keyscan3 for ?write? use if (keyscan1==1 & keyscan2==1 & keyscan3==1)i=4; // jump to break switch (i) { case 1: write( command, 0xd6 ); // vop offset +1 step break; case 2: write( command, 0xd7 ); // vop offset -1 step break; case 3: write_7636reeprom(); // write eeprom flow j=0; break; default: break; } } } c. write eeprom void write_7636reeprom(void) { write( command, 0x30 ); // ext=0 write( command, 0xae ); // display off write( command, 0x20 ); // power control write( data, 0x08 ); // b/f/r = on/off/off write( command, 0x8e ); // enable eeporm write mode write( command, 0x31 ); // ext=1 write( command, 0xeb ); // select eeprom write( data, 0x00 ); // eeprom 1st byte write( command, 0x31 ); // ext=1 write( command, 0xcd ); // control eeprom on write( data, 0x20 ); // write eeprom mode delay(50000); // delay 50 ms write( command, 0xfc ); // write data to eeprom
ST7636R ver 1.4 108/109 2006/09/06 delay(50000); // delay 50ms write( command, 0xeb ); // select eeprom write( data, 0x01 ); // eeprom 2nd byte write( command, 0x31 ); // ext=1 write( command, 0xcd ); // control eeprom on write( data, 0x20 ); // write eeprom mode delay(50000); // delay 50 ms write( command, 0xfc ); // write data to eeprom delay(50000); // delay 50ms write( command, 0xeb ); // select eeprom write( data, 0x02 ); // eeprom 3rd byte write( command, 0x31 ); // ext=1 write( command, 0xcd ); // control eeprom on write( data, 0x20 ); // write eeprom mode delay(50000); // delay 50 ms write( command, 0xfc ); // write data to eeprom delay(50000); // delay 50ms write( command, 0xeb ); // select eeprom write( data, 0x03 ); // eeprom 4th byte write( command, 0x31 ); // ext=1 write( command, 0xcd ); // control eeprom on write( data, 0x20 ); // write eeprom mode delay(50000); // delay 50 ms write( command, 0xfc ); // write data to eeprom delay(50000); // delay 50ms write( command, 0xeb ); // select eeprom write( data, 0x04 ); // eeprom 5th byte write( command, 0x31 ); // ext=1 write( command, 0xcd ); // control eeprom on write( data, 0x20 ); // write eeprom mode delay(50000); // delay 50 ms write( command, 0xfc ); // write data to eeprom delay(50000); // delay 50ms write( command, 0x31 ); // ext=1 write( command, 0xcc ); // cancel eeprom delay(50000); // delay 50ms write( command, 0x30 ); // ext=0 write( command, 0x8f ); // disable eeporm write mode write( command, 0x30 ); // ext=0 write( command, 0x20 ); // power control write( data, 0x0b ); // b/f/r = on/on/on write( command, 0xaf ); // display on } note: microprocessor interface pins should not be floating in any operation mode.
ST7636R ver 1.4 109/109 2006/09/06 ST7636R serial specification revision history version date description 0.x -- preliminary version 1.0 2006/03/24 to modify ?g 1. eeprom flow 2. application note for ito layout 3. command in extention enable/disable mode 1.1 2006/6/14 1. remove the resistor from vout in the application circuits 2. identify v4 < vdd-vdiode 3. identify the sequence of power on and power off 1.2 2006/8/14 add microprocessor notice item(p.16, p.108). 1.3 2006/9/5 modify the value of osc frequency and the bump size diagram of pad 485~604 and dummy pad 1.4 2006/9/6 modify the table of osc frequency adjustment

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